• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.47-50
• /
• 2000

DC Gummel-Poon SPICE model parameter extraction program has been implemented. This program extracts the parameters from measured data using Levenberg-Marquardt algorithm. Measured data consist of forward and reverse Gummel plot, forward and reverse output characteristics and RE and RC measurements.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.943-946
• /
• 2003

This paper proposes new SPICE Macro-Model of MTJ(Magnetic Tunnel Junction). This Macro-Model has five I/O terminals, reproduces MR characteristics including hysteresis and behaves correctly to time varying input signals. Furthermore, this Model can be easily modified to various MTJs with different characteristics by simply varying internal parameters.

• Proceedings of the Safety Management and Science Conference
• /
• 2005.05a
• /
• pp.129-135
• /
• 2005

This paper proposes the interated and balanced project management system for software and IT by considering BSC, MBNQA, ISO 9001, Six Sigma, CMM and SPICE. This system can be extended to assess the various project management practices.

• Proceedings of the Korea Multimedia Society Conference
• /
• 2003.05b
• /
• pp.733-736
• /
• 2003

최근 소프트웨어 프로세스 개선을 통하여 개발되는 소프트웨어의 품질을 향상시키기 위하여 개발 조직의 ?f발 능력과 생산성을 향상시키기 위하여 많은 회사들이 관심을 보이고 있다. 본 논문에서는 다양한 프로세스 심사 모델의 장점을 흡수하면서 조직 유형 및 프로젝트 규모에 제약 없이 프로세스 심사를 위한 개념을 제공하는 ISO/IEC 15504(SPICE)를 설명하고 최근의 심사사례를 바탕으로 전반적인 심사과정을 소개한다.

• Journal of the Institute of Convergence Signal Processing
• /
• v.2 no.3
• /
• pp.102-109
• /
• 2001

In this paper, a new multiplication algorithm which describes the methods of constructing a multiplierover GF(p$^{m}$ ) was presented. For the multiplication of two elements in the finite field, the multiplication formula was derived. Multiplier structures which can be constructed by this formula were considered as well. For example, both GF(3) multiplication module and GF(3) addition module were realized by current-mode CMOS technology. By using these operation modules the basic cell used in GF(3$^{m}$ ) multiplier was realized and verified by SPICE simulation tool. Proposed multipliers consisted of regular interconnection of simple cells use regular cellular arrays. So they are simply expansible for the multiplication of two elements in the finite field increasing the degree m.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.4
• /
• pp.21-29
• /
• 1998

As silicon geometry shrinks into deep submicron and the operating speed icreases, higher accuracy is required in the analysis of the propagation delays of the gates and interconnects in an ASIC. In this paper, the driving characteristics of a CMOS gate is represented by a gatedriver model, consisting of a linear resistor $R_{dr}$ and an independent ramp voltage source $V_{dr}$ . We drivered $R_{dr}$ and $V_{dr}$ as the functions of the timing data representing gate driving capability and an effective capacitance $C_{eff}$ reflecting resistance shielding effect by interconnet circuits. Through iterative applications of these equations and AWE algorithm, $R_{dr}$ , $V_{dr}$ and $C_{eff}$ are comuted simulataneously. then, the gate delay is decided by $C_{eff}$ and the interconnect circuit delay is determined by $R_{dr}$ and $V_{dr}$ . this process has been implemented as an ASIC timing analysis program written in C language and four real circuits were analyzed. In all cases, we found less than 5% of errors for both of gate andinterconnect circuit delays with a speedup factor ranging from a few tens to a few hundreds, compared to SPICE.SPICE.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.4
• /
• pp.65-72
• /
• 2013

This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Memristor-CMOS and is verified with SPICE-like Memristor model under $0.18{\mu}m$ CMOS technology. As a result, an example design Memristor-CMOS full adder has only 47.6 % of silicon area compare to the CMOS full-adder.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.7 s.349
• /
• pp.20-28
• /
• 2006

A new TWA(Traveling-wave-based Waveform Approximation)-based signal integrity verification method for practical interconnect layout structures which are composed of non-uniform RLC lines with various discontinuities is presented. Transforming the non-uniform lines into virtual uniform lines, signal integrity of the practical layout structures can be very efficiently estimated by using the TWA-technique. It is shown that the proposed technique can estimate the signal integrity much more efficiently than generic SPICE circuit model with 5% timing error and 10% crosstalk error.

• Journal of Sensor Science and Technology
• /
• v.23 no.4
• /
• pp.284-289
• /
• 2014

In this paper, modeling of a gate/body-tied (GBT) PMOSFET photodetector with built-in transfer gate is performed. It can control the photocurrent with a high-sensitivity. The GBT photodetector is a hybrid device consisted of a MOSFET, a lateral BJT, and a vertical BJT. This device allows for amplifying the photocurrent gain by $10^3$ due to the GBT structure. However, the operating parameters of this photodetector, including its photocurrent and transfer characteristics, were not known because modeling has not yet been performed. The sophisticated model of GBT photodetector using a process simulator is not compatible with circuit simulator. For this reason, we have performed SPICE modeling of the photodetector with reduced complexity using Cadence's Spectre program. The proposed modeling has been demonstrated by measuring fabricated chip by using 0.35 im 2-poly 4-metal standard CMOS technology.

• Journal of the Korea Computer Industry Society
• /
• v.2 no.12
• /
• pp.1533-1540
• /
• 2001

In this paper, we described extraction method of electrical parameters and modeling method of PCB nets on PCB design process. To analyze electrical characteristics of real PCB structure, we selected a cache memory system as an experimental board and designed 6 layer PCB substrate. For extraction of the electrical parameters, we divided circuit elements into the components of conductor types which are wires, via holes, BGA balls etc. and combined the calculated value by real net structure to modeling the PCB nets. We analyzed the electrical characteristics of the PCB nets with the simulation tools of SPICE and XNS. The simulation analysis has shown that the maximum signal delay was 2.6ns and the maximum crosstalk noise was 281 mV and we found that the designed substrate was adequate to system specification.