• 한국철도학회:학술대회논문집
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• 한국철도학회 2006년도 추계학술대회 논문집
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• pp.1468-1476
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• 2006

The goal of this thesis is to support safety and reliability characteristics of software intensive critical systems. The verification method developed is innovative from current state of the art in what concerns the verification viewpoint adopted: focusing on software faults, and not, like many other approaches purely on fulfilling functional requirements. As a first step and based on a number of well defined criteria a comparison was made of available literature in the area of static non formal non probabilistic software fault removal techniques. But, None of the techniques evaluated fulfilled all criteria set in isolation. Therefore a new technique was developed based on a combination of two existing techniques: the FMEA and FTA. These two techniques complement each other very well. It is possible to integrate both techniques with commonly used techniques at system level. The resulting new technique can be shown to combine nearly all aspects of existing fault removal techniques.

• 한국컴퓨터정보학회논문지
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• 제20권10호
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• pp.15-21
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• 2015

In this paper, we propose a stable automatic signature verification algorithm applicable to various smart devices. The proposed algorithm uses real and forgery data all together, which can improve the verification rate dramatically. As a tool for signature acquisition in a smart device, two applications, one using touch with a finger and the other using a pressure-sensing-stylus pen, are developed. The verification core is based on SVM and some modifications are made to include the characteristics of signatures. As shown in experimental results, the minimum error rate was 1.84% in the SVM based method, which can easily defeat 4.38% error rate with the previous parametric approach. Even more, 2.43% error rate was achieved with the features excluding pressure-related features, better than the previous approach including pressure-related features and only about 0.6% more error than the best result, which means that the proposed algorithm can be applied to a smart device with or without pressure-sensing-stylus pens and used for security purposes.

• 한국군사과학기술학회지
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• 제10권1호
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• pp.55-69
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• 2007

The paper provides the approach to apply formal methods to the development and certification criteria of defense safety/security-critical software. RTCA/DO-178B is recognized as a do facto international standard for airworthiness certification but lack of concrete activities and vagueness of verification/certification criteria have been criticized. In the case of MoD Def Stan 00-55, the guidelines based on formal methods are concrete enough and structured for the defense safety-related software. Also Common Criteria Evaluation Assurance Level includes the strict requirements of formal methods for the certification of high-level security software. By analyzing the problems of DO-178B and comparing it with MoD Def Stan 00-55 and Common Criteria, we identity the important issues In safety and security space. And considering the identified issues, we carry out merging of DO-178B and CC EAL7 on the basis of formal methods. Also the actual case studies for formal methods applications are shown with respect to the verification and reuse of software components.

• 한국항공우주학회지
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• 제42권5호
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• pp.398-405
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• 2014

내장형 소프트웨어 기술이 항공 및 방위산업과 같은 안전-필수 시스템에 적용됨에 따라 보다 높은 소프트웨어의 신뢰성이 요구되고 있다. 그 중에서 소프트웨어의 무결성은 주로 정적 분석 도구를 이용해 검증이 이뤄지고 있으며 최근에 개발된 정적 분석 도구는 수학적인 분석 방법을 통해 코드의 무결성을 평가하고 있다. 본 연구에서는 정형 검증 도구인 Polyspace를 이용해 자동코드의 결함을 검출하고, 코딩규칙의 준수 여부를 검증하였다. 검증된 결과를 바탕으로 결함을 가진 제어법칙 모델을 수정하여 코드 생성 이전의 원천적인 결함을 제거 가능함을 확인하였고 FBW 헬리콥터 제어법칙 자동생성코드의 무결성을 확보 할 수 있었다.

• 한국정보통신학회논문지
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• 제21권12호
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• pp.2298-2304
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• 2017

온라인 서명 검증은 간단하면서도 효율적인 본인 확인 방법의 하나로 다른 생체 인식 기술에 비해 거부감이 적은 장점이 있다. 서명 검증 모델을 학습하기 위해서는 모조서명이 필요하지만 대부분의 실용적인 응용에서는 모조서명을 확보하기가 쉽지 않다. 이 논문에서는 이러한 모조서명 확보 문제를 해결할 수 있는 방법의 하나로 다른 사람의 서명을 활용하는 방법을 제시한다. 검증 과정에서는 서명의 형태적 특징을 추출하고 이를 SVM을 이용하여 검증하였다. SVM은 특징 벡터를 고차원으로 사상하고 사상된 공간에서 선형 분리를 시도하는 방법으로 인식기 중 범용적이면서 높은 성능을 보이는 것으로 알려져 있다. 모델 생성 과정에서 모조서명으로 검증하고자 하는 사람의 서명과 형태적인 유사점을 찾을 수 없는 서명, 즉, 일반 필기 데이터를 사용함으로써, 모조서명의 확보가 어려운 경우에도 검증률을 개선할 수 있음을 실험 결과를 통해 확인할 수 있으며, 이는 모조서명 없이도 서명 검증이 가능함을 보여준다.

• ETRI Journal
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• 제30권1호
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• pp.141-151
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• 2008

In this paper, we introduce a new verification platform with ARM- and DSP-based multiprocessor architecture. Its simple communication interface with a crossbar switch architecture is suitable for a heterogeneous multiprocessor platform. The platform is used to verify the function and performance of a DVB-T baseband receiver using hardware and software partitioning techniques with a seamless hardware/software co-verification tool. We present a dual-processor platform with an ARM926 and a Teak DSP, but it cannot satisfy the standard specification of EN 300 744 of DVB-T ETSI. Therefore, we propose a new multiprocessor strategy with an ARM926 and three Teak DSPs synchronized at 166 MHz to satisfy the required specification of DVB-T.

• 전기학회논문지P
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• 제57권2호
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• pp.65-71
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• 2008

Recently, many critical control systems are developed using formal methods. When software applied to such systems is developed, the employment of formal methods in the software requirements specification and verification will provide increased. assurance for such applications. Earlier error of overlooked requirement specification can be detected using formal specification method. Also the testing and full verification to examine all reachable states using model checking to undertake formal verification are able to be completed. In this paper, we propose an eclectic approach to incorporate Z(Zed) formal language and 'Statemate MAGNUM' which is formal method tools using Statechart for applying to the railway signaling systems.

• Journal of Electrical Engineering and Technology
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• 제4권1호
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• pp.87-92
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• 2009

Many critical control systems are developed using formal methods. When software applied to such systems is developed, the employment of formal methods in the software requirements specification and verification will provide increased assurance for such applications. Earlier errors of overlooked requirement specification can be detected using the formal specification method. Also, the testing and full verification to examine all reachable states using model checking to undertake formal verification are able to be completed. In this paper, we proposed an eclectic approach to incorporate Z(Zed) formal language and 'Statemate MAGNUM', formal method tools using Statechart. Also we applied the proposed method to train control systems for the formal requirement specification and analyzed the specification results.

• International Journal of Computer Science & Network Security
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• 제24권4호
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• pp.192-196
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• 2024

The memory coherence problem occurs while mapping shared virtual memory in a loosely coupled multiprocessors setup. Memory is considered coherent if a read operation provides same data written in the last write operation. The problem is addressed in the literature using different algorithms. The big question is on the correctness of such a distributed algorithm. Formal verification is the principal term for a group of techniques that routinely use an analysis that is established on mathematical transformations to conclude the rightness of hardware or software behavior in divergence to dynamic verification techniques. This paper uses UPPAAL model checker to model the dynamic distributed algorithm for shared virtual memory given by K.Li and P.Hudak. We analyse the mechanism to keep the coherence of memory in every read and write operation by using a dynamic distributed algorithm. Our results show that the dynamic distributed algorithm for shared virtual memory partially fulfils its functional requirements.

• 제어로봇시스템학회논문지
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• 제14권8호
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• pp.824-836
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• 2008

Relaxed static stability(RSS) concept has been applied to improve aerodynamic performance of modern version supersonic jet fighter aircraft. Therefore, flight control systems are necessary to stabilize an unstable aircraft, and provides adequate handling qualities and achieve performance enhancements. Standard FCSDVP (Flight Control System Design and Verification Process) is provided to reduce development period of the flight control system. In addition, if this process is employed in developing flight control system, it reduces the trial and error for development and verification of flight control system. This paper addresses the flight control system design and verification process for the RSS aircraft utilizing design goal based on military specifications, linear and nonlinear system design and verification based on universal software, handling quality test based on HILS(Hardware In-the-Loop Simulator) environment, and ground and flight test results to verify aircraft dynamic flight responses.