• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.257-266
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• 2007

In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1432-1434
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• 2005

Single-stage converters are simpler and less expensive than convention two-stage converters. It can be a challenge, however, to design single-stage converters to satisfy certain key criteria such as input power factor, primary-side do bus voltage, and output voltage ripple. This is especially true for higher power single-stage AC/DC TTFC(Two-Transistor Forward Converter).

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.669-671
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• 2004

This paper presents a MIMO nonlinear controller for the power system consisting of a turbine and a synchronous generator connected to an infinite bus. The controller proposed is based on feedback input-output linearization; its main goal is to regulate the terminal voltage and frequency, and is to improve the transient stability under large disturbances and unexpected faults. It is guaranteed that the voltage converges to its reference value exponentially, and that the frequency and the mechanical/electrical power are bounded. The design procedure is tested on a single machine infinite bus power system through simulations, and is seen to be effective.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.450-451
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• 2008

The Bimodal tram is developed in KRRI (Korea Railroad Research Institute). This vehicle will be used in the public transportation system. The Bimodal tram has the advantages of both bus and train. Bus system has the advantages of flexibility of the routes delivering passengers to the destination and easy accessibility. Train is to meet the scheduled arrival and massive public transportations. The vehicle is the rubber tired tram and is all wheel steered single articulation. The vehicle can be automatically operated by navigation control system (NCS). For the automatic driving, the vehicle lanes will be marked with permanent magnets that are buried in the road. The control algorithm developed for navigation control has to be verified before being applied in the vehicle. In this purpose, we design the simulator for controller test of the bimodal tram.

• Proceedings of the KSRS Conference
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• v.1
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• pp.67-70
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• 2006

KARI is developing Image Data Acquisition and Control System (IDACS) for pre-processing meteorological and ocean data acquired on geostationary orbit. This paper describes the functions and architecture of IDACS and gives its operation policy including backup operation to overcome limitation of single-configured antenna system. The COMS IDACS provides the capability to receive the raw sensor data and disseminate processed MI data to users via a satellite. From the processed image data, users can produce a set of meteorological and ocean products for a wide range of applications. Most of IDACS subsystems are being developed by Korean technologies and experience acquired from previous projects. In case of COMS geometric correction software module, as it is closely dependent on the characteristics of imagers and spacecraft bus system, it is being co-developed with overseas prime contractor who develops spacecraft bus system.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1695-1696
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• 2008

KRRI (Korea Railroad Research Institute) is developing a bimodal tram since the 2003s. The vehicle will be used in the public transportation system. The bimodal tram has the advantages of both bus and train. Bus system has the advantages of flexibility of the routes delivering passengers to the destination and easy accessibility. Train is to meet the scheduled arrival and massive public transportations. The vehicle is the rubber tired tram and is all wheel steered single articulation. The propulsion system is configured by CNG hybrid system. The length of the vehicle is 18m. The vehicle lanes will be marked with permanent magnets that are buried in the road. The vehicle can be automatically operated by navigation control system (NCS). In this paper, we introduce the driving system of the bimodal tram which is developed by KRRI.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.6
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• pp.537-543
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• 2000

A novel integrated battery charger/discharger converter for a standardized battery module is proposed. Instead of using separate charger and discharger converters, it integrates these two converters into a single converter in order to minimize the size. The integrated charger/discharger converter not only regulates the solar array output power including the peak power tracking capability but also controls the battery charging/discharging current depending on the solar array output power and the load power. In addition, it offers a regulated bus voltage which simplifies the power distribution/conversion for the pay load.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.34 no.11
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• pp.421-429
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• 1985

With the rapid increase of contingency cases due to complication of power system, the reduction of computation time in contingency analysis has become more significant than ever before. This paper deals with the development of a fast contingency analysis algorithm by using a matrix decomposition method. The proposed matrix decomposition method of contingency analysis yields an accurate solution by using the original triangular factor table. An outstanding feature of this method is of no need of factor table modification for network changes due to contingency outages. The proposed method is also applicable to multiple contingency analysis withremarkable reduction of computation time. The algorithm has been tested for a number of single and multiple contigencies in 17-bus and 50-bus systems. The numerical results show its applicability to practical power systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.10
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• pp.2620-2633
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• 1996

In this paper, a new high-speed local area network using a dual mode switching access (DMSA) protocol implemented on a dual unidirectional bus is described. By utilizing the implicit positionalordering of stations on a unidirectional bus, the proposed system switches between random access mode and the token access model withoug unnecessary delay. Therefore, unlike other hybrid systems such as Buzz-net and Z-net, DMSA does not show a rapid degradation in performance as the load increases. We obtain the average channel utilization and the average access delay by using a simplified analytic model. The numerical results obtained via analysis are compared to the simulation resuls for a partial validation of the approximate model. The performance characteristics of DMSA are superior delay-throughput characteristics at light and medium loads, compared to compared to other LAN systems, and the capability of providing a single active station with full capabity of the channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.1
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• pp.28-40
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• 1988

Nowadays, the needs for intelligence of communication equipments and the cost down of micro processor are showing a tendency to have multi0processor in a single system. In this paper, based on the Reserved Bus Topology which is propoed in "A study on he Communication Method between the adjacent processor", the software and hardware is designed and developed. And tha validity of this method and the utility of designed software and hardware functions are also verified through exepriments.epriments.