• Journal of IKEEE
• /
• v.13 no.2
• /
• pp.101-107
• /
• 2009

Growth in the VLSI process and design technology is resulting into a continuous increase in the number of IPs on a chip to form a system. Because of many IPs on a single chip, efficient communication between IPs is essential. We propose a dynamically reconfigurable 3-layer bus structure which can adapt to the pattern of data transmission to achieve an efficient data communication between various IPs. The proposed 3-layer bus can be reconfigured to multi-single bus mode, and single-multi bus mode, thus providing the benefits of both single-bus and multi-bus modes. Experimental results show that the flexibility of the proposed bus structure can reduce data transmission time compared to the conventional fixed bus structure. We incorporated the proposed bus structure in a JPEG system and verified that the proposed structure achieved an average of 22% improvement in time over the conventional fixed bus structure.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.9
• /
• pp.96-102
• /
• 2008

The SoC bus topology is classified to single and multiple bus systems due to bus number. In single bus system, the selected only one master among the masters that try to initiate the bus transaction can execute its data transaction. On the other hand, in multiple bus system, as several buses that can be operated independently are connected with bridge, multiple data can be transferred parallel in each bus. However, In the case of data communication from one bus system to the other, data latency has remarkably increased in multiple bus. Furthermore, the performance of multiple bus can be easily different from master number, slave type and so on. In this paper, the performance of single and multiple bus architecture is compared and quantitatively analysed with the variation of master number and slave type especially a tying SDRAM, SRAM and register with TLM simulation method.

• Journal of Korean Society of Transportation
• /
• v.14 no.1
• /
• pp.69-80
• /
• 1996

In most cities, travel demand is distributed along long corridors and its destinations tend to concentrate in a central business district. For this kind of many-to-one or one-to-many travel demand pattern, a zonal operation of buses can be an efficient bus operation technique in which a long bus-demand corridor is divided into service zones and each service zone is provided with its own bus route connecting the service zone and single destination separately. This paper develops models of the total transportation costs for a single-zone operation and 2-zonal operation of buses for a long demand corridor with single destination in terms of various cost parameters, demand density, bus operation speeds, and location of the boundary between two service zones. In this study the total transportation cost is assumed to consist of the bus operation cost, passenger waiting cost and passenger travel time cost. It was proved that a zonal operation of buses can be more efficient than a single-zone operation for certain circumstances of the system and an boundary condition between two operation techniques was obtained. Also, several case studies were performed for various values of the cost parameters.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.1
• /
• pp.94-101
• /
• 2010

Optimization of interconnects among processors and memories becomes important as multiple processors and memories can be integrated on a Multi-Processor System-on-Chip (MPSoC). Since the optimal interconnection architecture is usually dependent on the applications, systematic design methodology for various data transfer requirements is necessary. In this paper, we focus on bus interconnection for MPSoC applications which use 4 ~ 16 processors. We propose a new systematic bus design methodology under performance constraints using Single Arbitration Multiple Bus Accesses (SAMBA) style bus architectures. Optimized bus architecture is found to satisfy performance constraints for a single or multiple applications. When compared to the unoptimized architecture, our method can reduce the bus switch logic circuits significantly (by more than 50% sometimes). Furthermore, low cost bus architectures can be found to satisfy the performance constraints for multiple applications.

• Journal of Navigation and Port Research
• /
• v.27 no.4
• /
• pp.479-484
• /
• 2003

In the case of the feeder bus route choice, it is more desirable to choose the route by treating as a single route linked from origin to destination than the whole network. This study is to establish a concept that frames the feeder bus route choice technique for the change of the existing single bus route or the creation of the new feeder bus route. The concept of the feeder bus route choice technique in this study is not to frame the whole bus network but to frame a single route to a unit O-D pair. So, this study has the assumption that does not consider the waiting and transfer time at the bus stop. This system technique consists of the following phases: I) limitation of the road network examined for the study, ii) enumeration of the appropriate candidate routes by the permissive route length, and iii) determination of the optimum bus route by the route evaluation value.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.27 no.2
• /
• pp.126-133
• /
• 2022

This study proposes a suppression of zero sequence current (ZSC), which is caused by zero sequence voltage (ZSV) for a dual two-level inverter with single DC bus. Large output voltages enable the dual inverter with single DC bus to improve a system efficiency compared with single inverter. However, the structure of dual inverter with single DC bus inevitably generates ZSC, which reduces the system efficiency and causes a current ripple. ZSV is also produced by dead time, and its magnitude is determined by the DC bus and current direction. This study presents a novel space vector modulation method that allows the instantaneous suppression of ZSC. Based on a condition where a switching period is twice a sampling (control) period, the proposed control method is implemented by injecting the offset voltage at the primary inverter. This offset voltage is injected in half of the switching period to suppress the ZSC. Simulation and experiments are used to compare the proposed and conventional methods to determine the ZSC suppression performance.

• Journal of the Korea Society for Simulation
• /
• v.3 no.1
• /
• pp.29-42
• /
• 1994

The architecture of a MIMD-type parallel computer system is specified: a simulator is developed to support design and evaluation of systems based on the architecture: and conducted with the simulator to evaluate system performance. The horizontal/vertical-bus(H/V-bus) system architecture provides an NxN array of processing elements which communicate with each other through a network of N horizontal buses and N vertical buses. The simulator, written in SLAM II and FORTRAN, is designed to provide high-resolution in simulating the IPC mechanism. Parameters provide the user with independent control of system size, PE speed and IPC mechanism speed. Results generated by the simulator include execution times, PE utilizations, queue lengths, and other data. The simulator is used to study system performance when a partial differential equation is solved by parallel Gauss-Seidel method. For comparisons, the benchmark is also executed on a single-bus system simulator that is derived from the H/V-bus system simulator. The benchmark is also solved on a single PE to obtain data for computing speedups. An extensive analysis of results is presented.

• Proceedings of the KIEE Conference
• /
• 2001.07a
• /
• pp.458-460
• /
• 2001

This paper described the unbalanced voltage on the tertiary bus of a single Phase auto transformer in the case of parallel operation with different manufacturer at each Phase. The unbalanced capacitances between primary to secondary winding, secondary to tertiary winding and primary to tertiary winding makes unbalanced bus voltage in the tertiary bus side. The unbalanced voltage let the surge arrester to operate in the power frequency range, and it causes the arrester to burn out. The failure of the arrester at one phase makes line to ground fault, which lead to the surge arrester failure of the other two phase on the tertiary bus.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.1
• /
• pp.224-240
• /
• 1996

It is common sense for at least one or more levels of cache memory to be used in these day's computer systems. In this paper, the impact of the internal cache memory organization on the performance of the computer is investigated by using a simulator program, which is wirtten by authors and run on SUN SPARC workstation, with several real execution, with several real execution trace files. 280 cache organizations have been simulated using n-way set associative mapping and LRU(Least Recently Used) replacement algorithm with write allocation policy. As a result, 16-way setassociative cache is the best configuration, and when we select 256KB cache memory and 64 byte line size, the bus traffic ratio was decreased compared to that of the noncache system so that a single bus could support almost 7 processors without any delay and degradationof high ratio(hit ratio was 99.21%). The smaller the line size we choose, the little lower hit ratio we can get, but the more processors can be supported by a single bus(maximum 18 processors). Therefore, using a proper cache memory organization can make a single bus structure be able to support multiple processors without any performance degradation.

• Journal of Electrical Engineering and Technology
• /
• v.9 no.2
• /
• pp.379-389
• /
• 2014

Low frequency oscillations (LFOs) are load angle oscillations that have a frequency between 0.1-2.0 Hz. Power system stabilizers (PSSs) are very effective controllers in improvement of the damping of LFOs. PSSs are designed by linearized models of the power system. This paper presents a new model of the power system that has the advantages of the Single Machine Infinite Bus (SMIB) system and the multi machine power system. This model is named a single machine normal-bus (SMNB). The equations that describe the proposed model have been linearized and a lead PSS has been designed. Then, particle swarm optimization technique (PSO) is employed to search for optimum PSS parameters. To analysis performance of PSS that has been designed based on the proposed model, a few tests have been implemented. The results show that designed PSS has an excellent capability in enhancing extremely the dynamic stability of power systems and also maintain coordination between PSSs.