• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.428-431
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• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the IEEK Conference
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• summer
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• pp.209-212
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• 2004

In this paper, The stress induced leakage currents of thin silicon oxides is investigated in the nano scale structure implementation for Soc. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41\square\;and\;113.4\square,$ which have the channel width x length 10x1um, respectively. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• Journal of Korean Ophthalmic Optics Society
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• v.19 no.3
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• pp.315-322
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• 2014

Purpose: The physical and optical characteristics of hydrophilic tinted contact lens containing titanium silicon oxide nanoparticles and the basic hydrogel contact lens material containing 4-iodoaniline were examined. In this study, the utility of titanium silicon oxide nanoparticles as a UV-blocking material for ophthalmologic devices were investigated by measuring the UV transmittance of the produced polymer. Also, titanium silicon oxide nanoparticles only without the addition of 4-iodoaniline in primary contact lens materials by copolymerizing two groups were compared. Methods: For manufacturing hydrogel lens, HEMA, MA, MMA, 4-iodoaniline and a cross-linker EGDMA were copolymerized in the presence of AIBN as an initiator. Also, the titanium silicon oxide nanoparticles was used as additive. After polymerization the physical properties such as water content, refractive index, contact angle and spectral transmittance of produced contact lenses were measured. Results: Measurement of the physical properties of the copolymerized material showed that the water content, refractive index, UV-B transmittance and contact angle were in the range of 35.01~38.60%, 1.4350~1.4418, $34.15{\sim}57.25^{\circ}$ and 1.0~10.0%, respectively. Titanium silicon oxide nanoparticles is not used as an additive in the experimental group, the results of the measurement showed that the water content, refractive index, contan angle and UV-B transmittance of the hydrogel lens polymer was 34.00~36.80%, 1.4378~1.4420, $40.15{\sim}60.16^{\circ}$ and 1.8~25.0%, respectively. Conclusions: Also, the transmittance for UV light was reduced significantly in combinations containing titanium oxide nanoparticles.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.335-340
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• 2002

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4${\AA}$ and 814${\AA}$, which have the gate area $10^3cm^2$. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Journal of the Korean institute of surface engineering
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• v.51 no.3
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• pp.185-190
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• 2018

Dopant-free silicon heterojunction solar cells using Transition Metal Oxide(TMO) such as Molybdenum Oxide($MoO_X$) and Vanadium Oxide($V_2O_X$) have been focused on to increase the work function of TMO in order to maximize the work function difference between TMO and n-Si for a high-efficiency solar cell. One another way to increase the work function difference is to control the silicon wafer resistivity. In this paper, dopant-free silicon heterojunction solar cells were fabricated using the wafer with the various resistivity and analyzed to understand the effect of n-Si work function. As a result, it is shown that the high passivation and junction quality when $V_2O_X$ deposited on the wafer with low work function compared to the high work function wafer, inducing the increase of higher collection probability, especially at long wavelength region. the solar cell efficiency of 15.28% was measured in low work function wafer, which is 34% higher value than the high work function solar cells.

• Journal of the Korean institute of surface engineering
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• v.55 no.3
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• pp.143-155
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• 2022

Ceramic oxide layers successfully were formed on the surface of cast Al alloys with high Si contents using plasma electrolytic oxidation (PEO) process in electrolytes containing Na₂SiO₃, NaOH, and additives. The microstructure of the oxide layers was systematically analyzed using scanning electron microscopy (SEM), cross-sectional transmission electron microscopy (TEM), X-ray diffraction patterns (XRD), and energy X-ray dispersive spectroscopy (EDS). XRD analysis indicated that the PEO untreated high-silicon Al alloys (i.e., 17.1 and 11.7 wt.% Si) consist of Al, Si and Al₂Cu phases whereas Al₂Cu phase selectively disappeared after PEO treatment. PEO process yielded an amorphous oxide layer with few second phases including γ-Al₂O₃ and Fe-rich phases. The corrosion behaviors of high-silicon Al alloys treated by PEO process were investigated using electrochemical impedance spectroscopy (EIS) and other electrochemical techniques (i.e., open circuit potential and polarization curve). Electroanalytical studies indicated that high-silicon Al alloys treated by PEO process have greater corrosion resistance than high-silicon alloys untreated by PEO process.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.05a
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• pp.310-316
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• 2002

In this study, the effects of oxide layer formed on the wear tracks of TiN coated silicon wafer on friction and wear characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with $1{\mu}m$ in coating thickness. AISI 52100 steel ball was used for the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction and wear characteristics using X-ray diffraction (XRD). Auger electron spectroscopy (AES), scanning electron microscopy (SEM) and sliding tests.

• Journal of the Korean Ceramic Society
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• v.39 no.7
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• pp.693-698
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• 2002

Reaction-Bonded Silicon Carbide (RBSC) Ceramics were fabricated which satisfies the maximum packing density of silicon carbide skeleton in the green compacts. Such a high packing density induced incomplete infiltration during reaction-sintering; forms linear void around the interface of large alpha silicon carbide powders. During reaction-sintering, the limited extraction and entrapped gas induced by residue oxide was considered to be a reason of linear void formation. In order to improve infiltration behavior in the highly packed preform, the pre-treatment methods for residue oxide removal were proposed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.125-130
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• 2000

Two step growth of reduced pressure chemical vapor eposition has been successfully developed to achieve in-situ phosphorus-doped silicon epilayers, and the characteristic evolution on their microstructures has been investigated using scanning electron microscopy, transmission electron microscopy, and secondary ion mass spectroscopy. The two step growth, which employs heavily in-situ P doped silicon buffer layer grown at low temperature, proposes crucial advantages in manipulating crystal structures of in-situ phosphorus doped silicon. In particular, our experimental results showed that with annealing of the heavily P doped silicon buffer layers, high-quality epitaxial silicon layers grew on it. the heavily doped phosphorus in buffer layers introduces into native oxide and plays an important role in promoting the dispersion of native oxides. Furthermore, the phosphorus doping concentration remains uniform depth distribution in high quality single crystalline Si films obtained by the two step growth.

• Korean Journal of Materials Research
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• v.14 no.1
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• pp.9-12
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• 2004

Metallic impurities, such as Fe, Cu, and Au, become generation and recombination centers for minority carriers when combined with oxide precipitates or silicon self-interstitial clusters. As these centers may cause leakage and discharge in silicon devices, their prevention through gettering of the metallic impurities is an important issue. In this article, key aspects of intrinsic gettering, such as oxygen control, wafer cleaning, device area denudation, and bulk oxygen precipitation are discussed, and a practical method of implementing intrinsic gettering is outlined.