• Korean Journal of Materials Research
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• v.10 no.4
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• pp.276-281
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• 2000

Silicon carbide(SiC) films were grown on modified Si(111) surface with a SiNx in the NH$_3$surrounding. Thickness of SiC films was decreased with increasing of the nitridation time. Also, voids having crystal defects were removed at interface of SiC/Si according to growth parameters. SiC films were grown on SiNx/Si substrate of 100, 300 and 500nm thickness. SiC films were deposited along [111] direction and columnar grains of SiC crystal. The void-free film was observed in the interface of SiC/SiNx. This result suggests that fabrication of SiC devices are applied to SiNx replacing silicon oxide in SOI structure.

• ETRI Journal
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• v.19 no.1
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• pp.26-35
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• 1997

The substrate effects on solid-phase crystallization of amorphous silicon (a-Si) films deposited by low-pressure chemical vapor deposition (LPCVD) using $Si_2H_6$ gas have been extensively investigated. The a-Si films were prepared on various substrates, such as thermally oxidized Si wafer ($SiO_2$/Si), quartz and LPCVD-oxide, and annealed at 600$^{\circ}C$ in an $N_2$ ambient for crystallization. The crystallization behavior was found to be strongly dependent on the substrate even though all the silicon films were deposited in amorphous phase. It was first observed that crystallization in a-Si films deposited on the $SiO_2$/Si starts from the interface between the a-Si and the substrate, so called interface-interface-induced crystallization, while random nucleation process dominates on the other substrates. The different kinetics and mechanism of solid-phase crystallization is attributed to the structural disorderness of a-Si films, which is strongly affected by the surface roughness of the substrates.

• Journal of the Korean Ceramic Society
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• v.31 no.5
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• pp.561-571
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• 1994

For the preparation of SiC composite, the properties of reaction sintering in the SiC-C-Si-Ti system with the titanium contents variation were investigated. Either the case of titanium additions or the case of direct infiltration of titanium in SiC+C preform, the newly formed fine-grained $\beta$-SiC, which was reacted from the molten silicon with graphite, was intergranulated between the original $\alpha$-SiC particles. Also titanium disilicide (TiSi2) was discontinuously formed isolated pocket in silicon matrix. The amount of titanium disilicide was gradually increased as titanium content increase. With the results of hardness and fracture toughness measurement, SiC-titanium disilicide (TiSi2) composite represented high properties compared with the system of the infiltrated pure silicon.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.147-150
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• 2003

In this paper, We fabricated a high temperature pressure sensor using SBD(silicon- direct-bonding) wafer of $Si/SiO_2$/Si-sub structure. This sensor was very sensitive because the piezoresistor is fabricated by single crystal silicon of the first layer of SDB wafer. Also, it was possible to operate the sensor at high temperature over $120^{\circ}C$ which is the temperature limitation of general silicon sensor because the piezoresistor was dielectric isolation from silicon substrate using silicon dioxide of the second layer. The sensitivity of this sensor is very high as the measured result of D2200 shows $183.6\;{\mu}V/V{\cdot}kPa$. Also, the output characteristic of linearity was very good. This sensor was available at high temperature as $300^{\circ}C$.

• Journal of Sensor Science and Technology
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• v.13 no.3
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• pp.175-181
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• 2004

A pressure sensor for high temperature was fabricated by using a SDB(Silicon-Direct-Bonding) wafer with a Si/$SiO_{2}$/ Si structure. High pressure sensitivity was shown from the sensor using a single crystal silicon of the first layer as a piezoresistive layer. It also was made feasible to use under the high temperature as of over $120^{\circ}C$, which is generally known as the critical temperature for the general silicon sensor, by isolating the piezoresistive layer dielectrically and thermally from the silicon substrate with a silicon dioxide layer of the second layer. The pressure sensor fabricated in this research showed very high sensitivity as of $183.6{\mu}V/V{\cdot}kPa$, and its characteristics also showed an excellent linearity with low hysteresis. This sensor was usable up to the high temperature range of $300^{\circ}C$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.111-114
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• 2008

We studied the influence of nanocrystalline silicon (nc-Si) thin film thickness on top gate nc-Si thin film transistor (TFT) fabricated at $180^{\circ}C$. The nc-Si thickness affects the characteristics of nc-Si TFT due to the nc-Si growth similar to a columnar. As the thickness of nc-Si increases from 40 nm to 200 nm, the grain size was increased from 20 nm to 40 nm. Having a large grain size, the thick nc-Si TFT surpasses the thin nc-Si TFT in terms of electrical characteristics such as field effect mobility. The channel resistance was decreased due to growth of the grain. We obtained the experimental results that the field effect mobility of the fabricated devices of which nc-Si thickness is 60, 90 and 130 nm are 26, 77 and $119\;cm^2/Vsec$, respectively. The leakage current, however, is increased from $7.2{\times}10^{-10}$ to $1.9{\times}10^{-8}\;A$ at $V_{GS}=-4.4\;V$ when the nc-Si thickness increases. It is originated from the decrease of the channel resistance.

• Journal of the Korean Ceramic Society
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• v.45 no.5
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• pp.285-289
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• 2008

Porous self-bonded silicon carbide (SiC) ceramics were fabricated at temperatures ranging from 1750 to $1850^{\circ}C$ using SiC, silicon (Si), and carbon (C) powders as starting materials. The effect of the Si:C ratio on porosity and strength was investigated as a function of sintering temperature. It was possible to produce self-bonded SiC ceramics with porosities ranging from 36% to 43%. The porous ceramics showed a maximal porosity when the Si:C ratio was 2:1 regardless of the sintering temperature. In contrast, the maximum strength was obtained when the ratio was 5:1.

• Journal of Korea Foundry Society
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• v.15 no.6
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• pp.566-573
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• 1995

In this study, the microstructural characteristics such as primary silicon, eutectic silicon, $SiC_p$ dispersion behavior, compound amount and Si solubility in $Al/SiC_p$ composite fabricated by the squeeze casting under various conditions were investigated systematically. As applied pressure(MPa) increases, cooling rate and compound amount are increased. In gravity casting, the cooling rate of hypereutectic composite is slower than of hypoeutectic composite by exothermic reaction of primary Si crystallization. But the cooling rate of hypereutectic composite is faster than that of hypoeutectic composite fabricated by same applied pressure, because amount of primary Si crystallization in hypereutectic composite was decreased, on the contrary, primary ${\alpha}-Al$ in hypoeutetic composite was increased due to increase of Si solubility in matrix by applied pressure. The crystalized primary silicon in hypereutectic composite fabricated by squeeze casting become more fine than that in non-pressure casting This is because mush zone became narrow due to increase of Si content of eutectic composition by pressure and time for growth of primary silicon got shorter according to applied pressure. It is turned out that eutectic temperature and liquidus are decreased by the increasing of squeeze pressure in all the composite due to thermal unstability of matrix owing to increasing of Si solubility in matrix by the increasing of applied pressure, as indicated in thermal anaiysis(DSC) results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.4
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• pp.809-815
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• 2000

The box capacitor structure with HSG-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a $0.4820\mum^2$ for 128Mbit DRAM. An HSG-Si formation technology with seeding method, which employs Si2H6 molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.The box capacitor structure with HSG-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a $0.4820\mum^2$ for 128Mbit DRAM. An HSG-Si formation technology with seeding method, which employs Si2H6 molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.