• 한국태양에너지학회:학술대회논문집
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• 2009.04a
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• pp.230-234
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• 2009

It is significant technique to increase competitiveness that solar cells have a high energy conversion efficiency and cost effectiveness. When making high efficiency crystalline Si solar cells, evaporated Ti/Pd/Ag contact system is widely used in order to reduce the electrical resistance of the contact fingers. However, the evaporation process is no applicable to mass production because high vacuum is needed. Furthermore, those metals are too expensive to be applied for terrestrial applications. Ni/Cu/Ag contact system of silicon solar cells offers a relatively inexpensive method of making electrical contact. Ni silicide formation is one of the indispensable techniques for Ni/Cu/Ag contact sytem. Ni was electroless plated on the front grid pattern, After Ni electroless plating, the cells were annealed by RTP(Rapid Thermal Process). Ni silicide(NiSi) has certain advantages over Ti silicide($TiSi_2$), lower temperature anneal, one step anneal, low resistivity, low silicon consumption, low film stress, absence of reaction between the annealing ambient. Ni/Cu/Ag metallization scheme is an important process in the direction of cost reduction for solar cells of high efficiency. In this article we shall report an investigation of rapid thermal silicidation of nickel on silngle crystalline silicon wafers in the annealing range of $350-390^{\circ}C$. The samples annealed at temperatures from 350 to $390^{\circ}C$ have been analyzed by SEM(Scanning Electron Microscopy).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.198-201
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• 2002

In this paper, the dependence of Ni-silicide properties such as sheet resistance and cross-sectional profile on the dopants have been characterized. There was little dependence of sheet resistance on the used dopants such as As, P, $BF_{2}$ and $B_{11}$ just after RTP (Rapid Thermal Process). However, the silicide properties showed strong dependence on the dopants when thermal treatment was applied after formation of Ni-silicide. $BF_{2}$ implanted sample shows the best stable property, while $B_{11}$ implanted one was thermally unstable. The main reason of the excellent property of $BF_{2}$ sample is believed to be the retardation of Ni diffusion by the flourine.

• Korean Journal of Materials Research
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• v.1 no.2
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• pp.99-104
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• 1991

Trantalum thin films have been prepared by DC sputtering onto As, P, and $BF_2$-implanted ($5{\times}10^15cm^-2$) poly-silicon. The heat treatments by rapid thermal annealing(RTA) have been applied to these samples for the formation of silicides. We have studied the application possibility of Ta-silicide as gate electrode and bit line. The silicide formation and the dopant diffusion after the heat treatment were investigated by various methods, such as four-point probe, X-ray, SEM cross sectional views, ${\alpha}$-step, and SIMS, The tantalum disilicide($TaSi_2$) are formed in the temperature above $800^{\circ}C$, and grown in colummar structure. $TaSi_2$ has a good surface roughness, having range from $80{\AA}\;to\;120{\AA}$, and implanted dopants are incoporated into the $TaSi_2$ layer during the RTA temperature.

• Korean Journal of Materials Research
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• v.8 no.10
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• pp.912-917
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• 1998

화학적 산화막(SiOx)이 형성된 Si(100)기판 위에 Co-silicide의 형성과 계면 형상에 관한 연구를 하였다. 화학적 산화막은 과산화수소수(H2O2)의 인위적 처리에 의해 약 2nm을 형성시켰다. 그 위에 5nm 두께의 Co 박막을 전자빔 증착기에 의해 증착시킨 후 열처리하여 Co-silicide를 형성하였다. 화학적 산화막 위에서 Co-silicide 반응기구를 알아 보기 위해 $500^{\circ}C$-$900^{\circ}C$의 온도 범위에서 ex-situ와 in-situ 열처리를 하였다. 이와같이 형성된 Co-silicide 시편의 상형성, 표면 및 계면 형상, 그리고 화학적 조성을 XRD, SEM, TEM, 그리고 AES를 이용하여 분석하였다. 분석 결과 es-situ 열처리시 $700^{\circ}C$까지 CoSi2 상은 형성되지 않았고 Co의 응집화현상이 일어났다. $800^{\circ}C$ 열처리한 경우에는 CoSI2가 형성되었고 facet 현상이 크게 나타났으며 불연속적인 grain 들이 형성되었다. In-situ 열처리한 경우에는 저온에서 ($550 ^{\circ}C$)반응하여 Co-silicide가 형성되기 시작하였으며 $600^{\circ}C$부터는 facet에 의해 박막의 특성이 나빠지기 시작했다. $550^{\circ}C$에서 Co가 화학적 산화막 층을 통해 확산하여 균질한 Co-silicide를 형성하였다. 이와같이 형성된 균질한 실리사이드 층을 이용하여 다단계(55$0^{\circ}C$-$650^{\circ}C$-$800^{\circ}C$)열처리에 의해 균질한 다결정 CoSI2의 형성이 관찰되었다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.3
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• pp.615-620
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• 2008

We fabriacted thermal evaporated $10nm-Ni_{1-x}Co_x$(x=0.2, 0.6, and 0.7) films on 70 nm-thick polysilicon substrate with $0.5{\mu}m$ line width. NiCo composite silicide layers were formed by rapid thermal annealing (RTA) at the temperatures of $700^{\circ}C$ and $1000^{\circ}C$. Then, we checked the microstructure evaluation of silicide patterns. A FIB (focused ion beam) was used to micro-mill the interconnect patterns with low energy condition (30kV-10pA-2 sec). We investigated the possibility of selective removal of silicide layers. It was possible to remove low resistance silicide layer selectively with the given FIB condition for our proposed NiCo composite silicides. However, the silicides formed from $Ni_{40}Co_{60}$ and $Ni_{30}Co_{70}$ composition showed void defects in interconnect patterns. Those void defects hinder the selective milling for the NiCo composite silicides.

• Korean Journal of Metals and Materials
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• v.46 no.3
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• pp.159-168
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• 2008

Thermally-evaporated 10 nm-Ni/1 nm-Ru/(30 nm or 70 nm-poly)Si structures were fabricated in order to investigate the thermal stability of Ru-inserted nickel monosilicide. The silicide samples underwent rapid thermal anne aling at $300{\sim}1,100^{\circ}C$ for 40 seconds. Silicides suitable for the salicide process were formed on the top of the single crystal and polycrystalline silicon substrates mimicking actives and gates. The sheet resistance was measured using a four-point probe. High resolution X-ray diffraction and Auger depth profiling were used for phase and chemical composition analysis, respectively. Transmission electron microscope and scanning probe microscope(SPM) were used to determine the cross-sectional structure and surface roughness. The silicide, which formed on single crystal silicon and 30 nm polysilicon substrate, could defer the transformation of $Ni_2Si $i and $NiSi_2 $, and was stable at temperatures up to $1,100^{\circ}C$ and $1,100^{\circ}C$, respectively. Regarding microstructure, the nano-size NiSi preferred phase was observed on single crystalline Si substrate, and agglomerate phase was shown on 30 nm-thick polycrystalline Si substrate, respectively. The silicide, formed on 70 nm polysilicon substrate, showed high resistance at temperatures >$700^{\circ}C$ caused by mixed microstructure. Through SPM analysis, we confirmed that the surface roughness increased abruptly on single crystal Si substrate while not changed on polycrystalline substrate. The Ru-inserted nickel monosilicide could maintain a low resistance in wide temperature range and is considered suitable for the nano-thick silicide process.

• Korean Journal of Metals and Materials
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• v.46 no.11
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• pp.762-769
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• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.11a
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• pp.52.2-52.2
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• 2007

• Proceedings of the Korean Ceranic Society Conference
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• 2000.10a
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• pp.159.2-159
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• 2000