• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.244.2-244.2
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• 2013

Contact Pattern을 Plasma Etching을 통해 Pattering 공정을 진행함에 있어서 Plasma 내에 존재하는 High Energy Ion 들의 Bombardment 에 의해, Contact Bottom 의 Silicon Lattice Atom 들은 Physical 한 Damage를 받아 Electron 의 흐름을 방해하게 되어, Resistance를 증가시키게 된다. 또한 Etchant 로 사용되는 Fluorine 과 Chlorine Atom 들은, Contact Bottom 에 Contamination 으로 작용하게 되어, 후속 Contact 공정을 진행하면서 증착되는 Ti 나 Co Layer 와 Si 이 반응하는 것을 방해하여 Ohmic Contact을 형성하기 위한 Silicide Layer를 형성하지 못하도록 만든다. High Aspect Ratio Contact (HARC) Etching 을 진행하면서 Contact Profile을 Vertical 하게 형성하기 위하여 Bias Power를 증가하여 사용하게 되는데, 이로부터 Contact Bottom에서 발생하는 Etchant 로 인한 Damage 는 더욱 더 증가하게 된다. 이 Damage Layer를 추가적인 Secondary Damage 없이 제거하기 위하여 본 연구에서는 원자층 식각방법(Atomic Layer Etching Technique)을 사용하였다. 실험에 사용된 원자층 식각방법을 이용하여, Damage 가 발생한 Si Layer를 Secondary Damage 없이 효과적으로 Control 하여 제거할 수 있음을 확인하였으며, 30 nm Deep Contact Bottom 에서 Damage 가 제거될 수 있음을 확인하였다. XPS 와 Depth SIMS Data를 이용하여 상기 실험 결과를 확인하였으며, SEM Profile 분석을 통하여, Damage 제거 결과 및 Profile 변화 여부를 확인하였으며, 4 Point Prove 결과를 통하여 결과적으로 Resistance 가 개선되는 결과를 얻을 수 있었다.

• 한국표면공학회지
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• 제32권3호
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• pp.389-392
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• 1999

We employed cobalt-disilicide for high-speed logic devices. We prepared stable and low resistant $CoSi_2$ through typical fabrication process including wet cleaning and rapid thermal process (RTP). We sputtered 15nm thick cobalt on the wafer and performed RTP annealing 2 times to obtain 60nm thick $CoSi_2$. We observed spherical shape voids with diameter of 40nm in the surface and inside $CoSi_2$ layers. The voids resulted in taking over abnormal junction leakage current and contact resistance values. We report that the voids in $CoSi_2$ layers are resulted from surface pits during the ion implantation previous to deposit cobalt layer. Silicide reaction rate around pits was enhanced due to Gibbs-Thompson effects and the volume expansion of the silicidation of the flat active regime trapped dimples. We confirmed that keeping the buffer oxide layer during ion implantation and annealing the silicon surface after ion implantation were required to prevent void defects in CoSi$_2$ layers.

• 대한금속재료학회지
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• 제48권7호
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• pp.660-666
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• 2010

30 nm thick Ni layers were deposited on a glass substrate by e-beam evaporation. Subsequently, 30 nm or 60 nm ${\alpha}-Si:H$ layers were grown at low temperatures ($<220^{\circ}C$) on the 30 nm Ni/Glass substrate by catalytic CVD (chemical vapor deposition). The sheet resistance, phase, microstructure, depth profile and surface roughness of the $\alpha-Si:H$ layers were examined using a four-point probe, HRXRD (high resolution Xray diffraction), Raman Spectroscopy, FE-SEM (field emission-scanning electron microscopy), TEM (transmission electron microscope) and AES depth profiler. The Ni layers reacted with Si to form NiSi layers with a low sheet resistance of $10{\Omega}/{\Box}$. The crystallinty of the $\alpha-Si:H$ layers on NiSi was up to 60% according to Raman spectroscopy. These results show that both nano-scale NiSi layers and crystalline Si layers can be formed simultaneously on a Ni deposited glass substrate using the proposed low temperature catalytic CVD process.

• 대한금속재료학회지
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• 제49권11호
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• pp.905-909
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• 2011

The formation of front metal contact silicon solar cells is required for low cost, low contact resistance to silicon surfaces. One of the available front metal contacts is Ni/Cu plating, which can be mass produced via asimple and inexpensive process. A selective emitter, meanwhile, involves two different doping levels, with higher doping (${\leq}30{\Omega}/sq$) underneath the grid to achieve good ohmic contact and low doping between the grid in order to minimize the heavy doping effect in the emitter. This study describes the formation of a selective emitter and a nickel silicide seed layer for the front metallization of silicon cells. The contacts were thickened by a plated Ni/Cu two-step metallization process on front contacts. The experimental results showed that the Ni layer via SEM (Scanning Electron Microscopy) and EDX (Energy dispersive X-ray spectroscopy) analyses. Finally, a plated Ni/Cu contact solar cell displayed efficiency of 18.10% on a $2{\times}2cm^2$, Cz wafer.

• 대한금속재료학회지
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• 제47권10호
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• pp.660-666
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• 2009

The consolidation of mechanical alloyed $Ti_5Si_3$ powder by electro-discharge-sintering has been investigated. A single pulse of 2.5 to 8.0 kJ/0.34 g was applied to each powder mixture using 300 and $450{\mu}F$ capacitors. A bulk-like solid with $Ti_5Si_3$ phase has been successfully fabricated by the discharge with an input energy of more than 2.5 kJ in less than $160{\mu}sec$. Micro-Vickers hardness was found to be higher than 1350, which is significantly higher than that of a conventional high temperature sintered sample. The formation of $Ti_5Si_3$ and consolidation occurred through a fast solid state diffusion reaction.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.572-578
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• 2014

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.

• 한국재료학회지
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• 제30권6호
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• pp.301-307
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• 2020

In this study, factors considered to be causes of promotion of densification of sintered pellets identified during phase change are reviewed. As a result, conclusions shown below are obtained for each factor. In order for MA powder to soften, a temperature of 1,000 K or higher is required. In order to confirm the temporary increase in density throughout the sintered pellet, the temperature rise due to heat during phase change was found not to have a significant effect. While examining the thermal expansion using the compressed powder, which stopped densification at a temperature below the MA powder itself, and the phase change temperature, no shrinkage phenomenon contributing to the promotion of densification is observed. The two types of powder made of Ti-silicide through heat treatment are densified only in the high temperature region of 1,000 K or more; it can be estimated that this is the effect of fine grain superplasticity. In the densification of the amorphous powder, the dependence of sintering pressure and the rate of temperature increase are shown. It is thought that the specific densification behavior identified during the phase change of the Ti-37.5 mol.%Si composition MA powder reviewed in this study is the result of the acceleration of the powder deformation by the phase change from non-equilibrium phase to equilibrium phase.

• 한국결정성장학회지
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• 제7권1호
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• pp.59-69
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• 1997

이트리움 실리사이드($YSi_2$)는 $400^{\circ}C$ 이상의 진공열처리 중 고상반응에 의하여 (100)Si 기판상에서 $YSi_2$의 (1100)면이 방향성 성장을 하였으며, $YSi_2$ 박막과 (100)Si 기판과의 방위관계는 [0001]$YSi_2$//[011i]Si과 [0001]$YSi_2$//[011]Si이었다. 그러나 방위관계에서도 알 수 있는 바와 같이 $YSi_2$는 [1100]$YSi_2$의 domain이 상호간에 $90^{\circ}$의 방위각을 이루며 성장하는 이른바 double-domain 구조를 나타내었다. 이는(1100)$YSi_2$면과 Si기판과의 계면에서 커다란 격자 불일치의 이방성 때문이라 생각되며, 각각의 domain은 (2201) 비대칭 반사면의 $\omega$-mode rocking curve 측정 결과, 거의 동등한 체적율과 결정성을 나타내었다. 본 연구에서는 이러한 double-domain의 형성기구를 (1100)$YSi_2$면과 (100)Si기판과의 계면에서 정합 모델에 근거한 기하학적 matching 관계로 설명하였다.

• 한국재료학회지
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• 제26권8호
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• pp.401-405
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• 2016

The cobalt silicides were investigated for employment as a catalytic layer for a DSSC. Using an E-gun evaporation process, we prepared a sample of 100 nm-thick cobalt on a p-type Si (100) wafer. To form cobalt silicides, the samples were annealed at temperatures of $300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$ for 30 minutes in a vacuum. Four-point probe, XRD, FE-SEM, and CV analyses were used to determine the sheet resistance, phase, microstructure, and catalytic activity of the cobalt silicides. To confirm the corrosion stability, we also checked the microstructure change of the cobalt silicides after dipping into iodide electrolyte. Through the sheet resistance and XRD results, we determined that $Co_2Si$, CoSi, and $CoSi_2$ were formed successfully by annealing at $300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$, respectively. The microstructure analysis results showed that all the cobalt silicides were formed uniformly, and CoSi and $CoSi_2$ layers were very stable even after dipping in the iodide electrolyte. The CV result showed that CoSi and $CoSi_2$ exhibit catalytic activities 67 % and 54 % that of Pt. Our results for $Co_2Si$, CoSi, and $CoSi_2$ revealed that CoSi and $CoSi_2$ could be employed as catalyst for a DSSC.

• 한국진공학회지
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• 제2권4호
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• pp.439-454
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• 1993

The phase sequence of codeposited Co-Si alloy and Co/si multilayer thin film was investigated by differential scanning calormetry(DSC) and X-ray diffraction (XRD) analysis, The phase sequence in codeposition and codeposited amorphous Co-Si alloy thin film were CoSilongrightarrow Co2Si and those in Co/Si multilayer thin film were CoSilongrightarrowCo2Silongrightarrow and CoSilongrightarrowCo2Si longrightarrowCoSilongrightarrowCoSi2 with the atomic concentration ration of Co to Si layer being 2:1 and 1:2 respectively. The observed phase sequence was analyzed by the effectvie heat of formatin . The phase determining factor (PDF) considering structural facotr in addition to the effectvie heat of formation was used to explain the difference in the first crystalline phase between codeposition, codeposited amorphous Co-Si alloy thin film and Co/Si multilayer thin film. The crystallinity of Co-silicide deposited by multitarget bias cosputter deposition (MBCD) wasinvestigated as a funcion of deposition temperature and substrate bias voltage by transmission electron microscopy (TEM) and epitaxial CoSi2 layer was grown at $200^{\circ}C$ . Parameters, Ear, $\alpha$(As), were calculate dto quantitatively explain the low temperature epitaxial grpwth of CoSi2 layer. The phase sequence and crystallinity had a stronger dependence on the substrate bias voltage than on the deposition temperature due to the collisional daxcade mixing, in-situ cleannin g, and increase in the number of nucleation sites by ion bombardment of growing surface.