• 반도체디스플레이기술학회지
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• 제18권3호
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• pp.82-87
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• 2019

One of the most critical aspects of the semiconductor industry is the quality of the wafer surface. And the vibrations of wafer grinder are supposed to be the most dominant factors to damage the wafer surface quality. In this study, structure of a wafer grinder has been analyzed through experiments and computer simulations to figure out the main reasons of the vibrations. And the design alterations based on the analysis were applied to identify the effects of those alterations on the vibration suppression. The result shows that the design alterations can effectively suppress about 90% of the vibrations.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.136-139
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• 2004

The requirement of planarity, such as with-in-wafer nonuniformity, post thickness range, have become increasingly stringent as critical dimensions of devices are decreased and a better control of a planarity become important. The key factors influencing the planarity capability of the CMP process have been well understood through numerous related experiments. These usually include parameters such as process pressures, relative velocities, slurry temperature, polishing pad materials and polishing head structure. Many study have been done about polishing pad and its groove structure because it's considered as one of the key factors which can decide wafer uniformity directly. But, not many study have been done about polisher head structure, especially about polisher head plate design. The purpose of this paper is to know how the plate structure can affect wafer uniformity and how to deteriorate wafer yield. Furthermore, we studied several new designed plate to improve wafer uniformity and also improve wafer yield.

• 한국정밀공학회지
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• 제20권2호
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• pp.218-225
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• 2003

The general dicing process cuts a semiconductor wafer to lengthwise and crosswise direction by using a rotating circular diamond blade. However, inferior goods may be made under the influence of several parameters in dicing process such as blade, wafer, cutting water and cutting conditions. Moreover we can not apply this dicing method to a GaN wafer, because the GaN wafer is harder than other wafers such as SiO$_2$, GaAs, GaAsP, and AlGaAs. In order to overcome this problem, development of a new dicing process and determination of dicing parameters are necessary. This paper describes determination of several parameters - scribing depth, scribing force, scriber inclined angle, scribing speed, and factor for scriber replacement - for a new dicing machine using a scriber.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2003년도 춘계학술대회 발표 논문집
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• pp.74-79
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• 2003

This paper is concerned with the estimation of a wafer part in grasping system. The estimation of a wafer size in grasping system is very important because a wafer must be placed in accurate position. The accurate information of a wafer size should be forward to Robot in order to place a wafer in accurate position. So in this paper, we decide the size of a wafer with Fuzzy Logic and consider the possibility of this method by simulation.

• 반도체디스플레이기술학회지
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• 제23권2호
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• pp.55-59
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• 2024

Plasma Enhanced Chemical Vapor Deposition (PE-CVD) is a widely used technology in semiconductor manufacturing for thin film deposition. The implementation of wafer guide rings in PE-CVD processes is crucial for enhancing efficiency and product quality by ensuring uniform deposition around wafer edges and reducing particle generation. On the other hand, to prevent overall temperature non-uniformity and degradation of thin film quality within the chamber, it is essential to consider various parameters comprehensively. In this study, after applying the wafer guide rings, temperature variations and fluid flow changes were simulated. Additionally, by simulating the temperature and flow changes when applied to the PE-CVD chamber, this paper discusses the importance of optimizing variables within the entire chamber.

• 한국시뮬레이션학회논문지
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• 제15권2호
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• pp.51-57
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• 2006

현재 반도체 산업은 200mm 웨이퍼에서 300mm 웨이퍼 공정으로 기술이 변화하고 있다. 300mm 웨이퍼 제조업체들은 Fabrication Line (FAB Line) 자동화를 비용절감 실현의 방책으로 사용하고 있다. 또한 기술의 확산, 시장 경쟁력의 격화 등으로 생산성 향상에 의한 원가절감이 반도체 산업 성장의 근본요인이 되고 있다. 대부분의 반도체 업체들은 생산성을 높이기 위해 average cycle time을 줄이는데 총력을 기울이고 있다. 본 논문에서는 average cycle time을 줄이는 데 중점을 두고, 300mm 반도체 제조공정을 시뮬레이션 하였다.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.108-112
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• 2023

Precision manufacturing technology is rapidly developing due to the extreme miniaturization of semiconductor processes to comply with Moore's Law. Accurate and precise alignment, which is one of the key elements of the semiconductor pre-process and post-process, is very important in the semiconductor process. The center detection of wafer align marks plays a key role in improving yield by reducing defects and research on accurate detection methods for this is necessary. Methods for accurate alignment using traditional image sensors can cause problems due to changes in image brightness and noise. To solve this problem, engineers must go directly into the line and perform maintenance work. This paper emphasizes that the development of AI technology can provide innovative solutions in the semiconductor process as high-resolution image and image processing technology also develops. This study proposes a new wafer center detection method through variable thresholding. And this study introduces a method for detecting the center that is less sensitive to the brightness of LEDs by utilizing a high-performance object detection model such as YOLOv8 without relying on existing algorithms. Through this, we aim to enable precise wafer focus detection using artificial intelligence.

• 산업공학
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• 제16권3호
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• pp.344-351
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• 2003

Critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, critical dimension control in a semiconductor wafer fabrication process is inevitable in order to achieve optimum device yield as well as electrically specified functions. Currently, in complex semiconductor wafer fabrication processes, statistical methodologies such as Shewhart-type control charts become crucial tools for practitioners. Meanwhile, given a critical dimension sampling plan, the analysis of variance technique can be more effective to investigating critical dimension variation, especially for on-chip and on-wafer variation. In this paper, relating to a typical sampling plan, linear statistical models are presented for the analysis of critical dimension variation. A case study is illustrated regarding a semiconductor wafer fabrication process.

• 반도체디스플레이기술학회지
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• 제5권2호
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• pp.41-46
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• 2006

Wet etching process in recent semiconductor manufacturing is devided into batch and single wafer type. Batch type wet etching process provides more throughput with poor etching uniformity compared to single wafer type process. Single wafer process achieves better etching uniformity by boom-swing injected chemical on rotating wafer. In this study, etching characteristics of $SiO_2$ layer at room and elevated temperature is evaluated and compared. The difference in etching rate and uniformity of each condition is identified, and the temperature profile of injected chemical is theoretically calculated and compared to that of experimental result. Better etching uniformity is observed with single wafer tool with boom-swing injection compared to single wafer process without boom-swing or batch type tool.

• 반도체디스플레이기술학회지
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• 제11권2호
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• pp.33-38
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• 2012

The wafer positioning robot in the semiconductor industry is required to operate at high speed for the improvement of productivity. The residual vibration caused by the high speed of the wafer positioning robot, however, makes the life of the robot shorter and the cycle time longer. In this study, the input shaping and the path of the system are designed for the reduction of the residual vibration and the improvement of the cycle time. The followings are the process for the reduction and the improvement; 1) System modeling of the wafer positioning robot, 2) Verification of dynamic characteristics of the wafer positioning robot, 3) Input shaping plan using impulse response reiteration, 4) Simulation test using SIMULINK program, 5) Analysis of result.