• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.4
• /
• pp.216-231
• /
• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Journal of the Semiconductor & Display Technology
• /
• v.4 no.1 s.10
• /
• pp.49-53
• /
• 2005

The nanoparticle deposition chamber, which is used for quantum dot semiconductor memory applications, is designed by means of numerical simulation. In this research, the numerical simulations for deposition chamber were performed by commercial software, FLUENT. The deposition of nanoparticles is calculated by diffusion force, thermophoresis and electrophoresis of particles. As a results, when the diffusion force was considered, the most of particles deposited in the wall of deposition chamber. But as considering thermophoresis and electrophoresis of particles, the particles were deposited wafer surface, perfectly.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2007.06a
• /
• pp.174-178
• /
• 2007

The cleaning process to remove small particles, ions, and other polluted sources is one of the major parts in the recent semiconductor industry because it can cause fatal errors on the quality of the final products. According to the other reports, the major factors of bath's fluid motion are the cleaning method, nozzle, the geometry (of bath, guide and wafer), and the position (of guide and wafer). So to enhance cleaning efficiency in the bath, these factors must be controlled. The purpose of this study is to analyze and visualize fluid motion in the cleaning bath as basic data for designing the nozzle system and finding the process control parameters. For that, we used the general CFD code FLUENT.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.29 no.11 s.242
• /
• pp.1463-1471
• /
• 2005

This paper proposes an agent-based scheduling method fur semiconductor wafer fabrication facilities with hard inter-operation temporal constraints. The scheduling problem is to find the feasible schedules that guarantee both logical and temporal correctness. A proposed multi-agent based architecture is composed of scheduling agents, workcell agents, and machine agents. A scheduling agent computes optimal schedules through bidding mechanisms with a subset or entire set of the workcell agents. A dynamic planning-based approach is adopted for the scheduling mechanism so that the dynamic behaviors such as aperiodic job arrivals and reconfiguration can be taken into consideration.

• Journal of the Semiconductor & Display Technology
• /
• v.11 no.3
• /
• pp.7-11
• /
• 2012

Among various wet cleaning methods, megasonic and jet spray gained their popularity in single wafer cleaning process for the efficient removal of particulate contaminants from the wafer surface. In the present study, we evaluated these two cleaning methods for particle removal efficiency (PRE) and pattern damage on the aluminum layered wafer surface. Also the effect of $CO_2$ dissolved water in jet spray cleaning is assessed by measuring PRE. It is observed that the jet spray cleaning process is more effective in terms of PRE and pattern damage compared to megasonic cleaning and the mixing of $CO_2$ in the water during jet sprays further increases the PRE. We believe that the outcome of the present study is useful for the semiconductor cleaning process engineers and researchers.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2006.05a
• /
• pp.555-556
• /
• 2006

In recent years, the higher flatness level in wafer shape has been strictly demanded with a high integration of the semiconductor devices. It has become difficult for a conventional wafer preparing process to satisfy those demands. In order to meet those demands, surface grinding with in-feed grinder is adopted. In an in-feed grinding method, a chuck table fur fixing a semiconductor wafrr rotates on its rotation axis with a slight tilt angle to the rotation axis of a cup shaped grinding wheel and the grinding wheel in rotation moves down to grind the wafer. So, stability of the grinder structure is very important to aquire a wafer of good quality. This paper describes the features of the in-feed grinder and some FEM analysis results of the grinder structure.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1998.08a
• /
• pp.78.2-78
• /
• 1998

• Composites Research
• /
• v.20 no.5
• /
• pp.49-55
• /
• 2007

Nanocomposite blade for dicing semiconductor wafer is investigated for micro/nano-device and micro/nano-fabrication. While metal blade has been used for dicing of silicon wafer, polymer composite blades are used for machining of quartz wafer in semiconductor and cellular phone industry in these days. Organic-inorganic material selection is important to provide the blade with machinability, electrical conductivity, strength, ductility and wear resistance. Maintaining constant thickness with micro-dimension during shaping is one of the important technologies fer machining micro/nano fabrication. In this study the fabrication of blade by wet processing of mixing conducting nano ceramic powder, abrasive powder phenol resin and polyimide has been investigated using an experimental approach in which the thickness differential as the primary design criterion. The effect of drying conduction and post pressure are investigated. As a result wet processing techniques reveal that reliable results are achievable with improved dimension tolerance.

• Journal of the Korean Operations Research and Management Science Society
• /
• v.18 no.1
• /
• pp.119-126
• /
• 1993

We study a manufacturing process that is quite common in semiconductor wafer fabrication of semiconductor chip production. A machine is used to process a job consisting of J wafers. Each job requires a setup, and the i$_{th}$ setup for a job is sucessful with probability P$_{i}$. The setup is prone to failure, which results in the loss of expensive wafers. Therefore, a tiral run is first conducted on a small batch. If the set up is successful, the test is passed and the balance of the job can be processed. If the setup is unsuccessful, the exposed wafers are lost to scrap and the mask is realigned. The process then repeats on the balance of the job. We call this as send-ahead policy and consider general policies in which the number of wafers that are sent shead depend on the cost of the raw wafer, the sequence of success probabilities, and the balance of the job. We model this process and determine the expected number of good wafers per job,the expected time to process a job, and the long run average throughput. An algorithm to minimize the cost per good wafer subject to a demand constraint is provided.d.d.

• Journal of the Semiconductor & Display Technology
• /
• v.15 no.1
• /
• pp.56-64
• /
• 2016

It is generally accepted that the surface quality of wafer edge is mostly damaged by the vibrations of the edge grinding machine. The surface quality of wafer edge is supposed to be the most dominant factor of the cracks, scratches, burrs and chips on the edge surfaces, which are the main defects of the wafers. In this study, the structure of a wafer edge grinder has been investigated through the frequency response experiment and the computer simulation to find ways to suppress the vibrations from the structure. The main reasons of the structural vibrations were analyzed. And further the design alterations were deduced from the results of the experiment and the simulation, and applied to the machine to check the effects of those alterations and to eventually improve the structural stability. The result shows that the machine can have much improved stability with relatively simple design changes.