• Title/Summary/Keyword: semiconductor device

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Enhanced Photosensitivity in Monolayer MoS2 with PbS Quantum Dots

  • Cho, Sangeun;Jo, Yongcheol;Woo, Hyeonseok;Kim, Jongmin;Kwak, Jungwon;Kim, Hyungsang;Im, Hyunsik
    • Applied Science and Convergence Technology
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    • v.26 no.3
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    • pp.47-49
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    • 2017
  • Photocurrent enhancement has been investigated in monolayer (1L) $MoS_2$ with PbS quantum dots (QDs). A metal-semiconductor-metal (Au-1L $MoS_2$-Au) junction device is fabricated using a standard photolithography method. Considerably improved photo-electrical properties are obtained by coating PbS QDs on the Au-1L $MoS_2$-Au device. Time dependent photoconductivity and current-voltage characteristics are investigated. For the QDs-coated $MoS_2$ device, it is observed that the photocurrent is considerably enhanced and the decay life time becomes longer. We propose that carriers in QDs are excited and transferred to the $MoS_2$ channel under light illumination, improving the photocurrent of the 1L $MoS_2$ channel. Our experimental findings suggest that two-dimensional layered semiconductor materials combined with QDs could be used as building blocks for highly-sensitive optoelectronic detectors including radiation sensors.

Integrate-and-Fire Neuron Circuit and Synaptic Device with Floating Body MOSFETs

  • Kwon, Min-Woo;Kim, Hyungjin;Park, Jungjin;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.6
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    • pp.755-759
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    • 2014
  • We propose an integrate-and-fire neuron circuit and synaptic devices with the floating body MOSFETs. The synaptic devices consist of a floating body MOSFET to imitate biological synaptic characteristics. The synaptic learning is performed by hole accumulation. The synaptic device has short-term and long-term memory in a single silicon device. I&F neuron circuit emulate the biological neuron characteristics such as integration, threshold triggering, output generation, and refractory period, using floating body MOSFET. The neuron circuit sends feedback signal to the synaptic transistor for long-term memory.

Characteristics of High Power Semiconductor Device Losses in 5MW class PMSG MV Wind Turbines

  • Kwon, Gookmin;Lee, Kihyun;Suh, Yongsug
    • Proceedings of the KIPE Conference
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    • 2014.07a
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    • pp.367-368
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    • 2014
  • This paper investigates characteristics of high power semiconductor device losses in 5MW-class Permanent Magnet Synchronous Generator (PMSG) Medium Voltage (MV) wind turbines. High power semiconductor device of press-pack type IGCT of 6.5kV is considered in this paper. Analysis is performed based on neutral point clamped (NPC) 3-level back-to-back type voltage source converter (VSC) supplied from grid voltage of 4160V. This paper describes total loss distribution at worst case under inverter and rectifier operating mode for the power semiconductor switches. The loss analysis is confirmed through PLECS simulations. In addition, the loss factors due to di/dt snubber and ac input filter are presented. The investigation result shows that IGCT type semiconductor devices generate the total efficiency of 97.74% under the rated condition.

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Schottky Barrier Tunnel Field-Effect Transistor using Spacer Technique

  • Kim, Hyun Woo;Kim, Jong Pil;Kim, Sang Wan;Sun, Min-Chul;Kim, Garam;Kim, Jang Hyun;Park, Euyhwan;Kim, Hyungjin;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.5
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    • pp.572-578
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    • 2014
  • In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.

A Study on the Field Ring of High Voltage Characteristics Improve for the Power Semiconductor (전력반도체 고내압 특성 향상을 위한 필드링 최적화 연구)

  • Nam, Tae-Jin;Jung, Eun-Sik;Jung, Hun-Suk;Kim, Sung-Jong;Kang, Ey-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.3
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    • pp.165-169
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    • 2012
  • Power semiconductor devices are widely used as high voltage applications to inverters and motor drivers, etc. The blocking voltage is one of the most important parameters for power semiconductor devices. And cause of junction curvature effects, the breakdown voltage of the device edge and device unit cells was found to be lower than the 'ideal' breakdown voltage limited by the semi-infinite junction profile. In this paper, Propose the methods for field ring design by DOE (Design of Experimentation). So The field ring can be improve for breakdown voltage and optimization.

Novel Punch-through Diode Triggered SCR for Low Voltage ESD Protection Applications

  • Bouangeune, Daoheung;Vilathong, Sengchanh;Cho, Deok-Ho;Shim, Kyu-Hwan;Leem, See-Jong;Choi, Chel-Jong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.6
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    • pp.797-801
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    • 2014
  • This research presented the concept of employing the punch-through diode triggered SCRs (PTTSCR) for low voltage ESD applications such as transient voltage suppression (TVS) devices. In order to demonstrate the better electrical properties, various traditional ESD protection devices, including a silicon controlled rectifier (SCR) and Zener diode, were simulated and analyzed by using the TCAD simulation software. The simulation result demonstrates that the novel PTTSCR device has better performance in responding to ESD properties, including DC dynamic resistance and capacitance, compared to SCR and Zener diode. Furthermore, the proposed PTTSCR device has a low reverse leakage current that is below $10^{-12}$ A, a low capacitance of $0.07fF/mm^2$, and low triggering voltage of 8.5 V at $5.6{\times}10^{-5}$ A. The typical properties couple with the holding voltage of 4.8 V, while the novel PTTSCR device is compatible for protecting the low voltage, high speed ESD protection applications. It proves to be good candidates as ultra-low capacitance TVS devices.

Device characteristics of 2.5kV Gate Commutated Thyristor (2-5kV급 Gate Commutated Thyristor 소자의 제작 특성)

  • Kim, Sang-Cheol;Kim, Hyung-Woo;Seo, Kil-Soo;Kim, Nam-Kyun;Kim, Eun-Dong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.280-283
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    • 2004
  • This paper discribes the design concept, fabrication process and measuring result of 2.5kV Gate Commutated Thyristor devices. Integrated gate commutated thyristors(IGCTs) is the new power semiconductor device used for high power inverter, converter, static var compensator(SVC) etc. Most of the ordinary GTOs(gate turn-off thyristors) are designed as non-punch-through(NPT) concept; i.e. the electric field is reduced to zero within the N-base region. In this paper, we propose transparent anode structure for fast turn-off characteristics. And also, to reach high breakdown voltage, we used 2-stage bevel structure. Bevel angle is very important for high power devices, such as thyristor structure devices. For cathode topology, we designed 430 cathode fingers. Each finger has designed $200{\mu}m$ width and $2600{\mu}m$ length. The breakdown voltage between cathode and anode contact of this fabricated GCT device is 2,715V.

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Performance Optimization of LDMOS Transistor with Dual Gate Oxide for Mixed-Signal Applications

  • Baek, Ki-Ju;Kim, Yeong-Seuk;Na, Kee-Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.16 no.5
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    • pp.254-259
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    • 2015
  • This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (RON) and 50% drain conductance (gds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.

Blazed $GxL^{TM}$ Device for Laser Dream Theatre at the Aichi Expo 2005

  • Ito, Yasuyuki;Saruta, Kunihiko;Kasai, Hiroto;Nshida, Masato;Yamaguchi, Masanari;Yamashita, Keitaro;Taguchi, Ayumu;Oniki, Kazunao;Tamada, Hitoshi
    • Journal of Information Display
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    • v.8 no.2
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    • pp.10-14
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    • 2007
  • A blazed $GxL^{TM}$ device is described as having high optical efficiency (> 70% for RGB lasers), and high contrast ratio (> 10,000:1), and that is highly reliable when used in a large-area laser projection system. It has a robust design and precise stress control technology to maintain a uniform shape (bow and tilt) of more than 6,000 ribbons, a $0.25-{\mu}m$ CMOS compatible fabrication processing and planarization techniques to reduce fluctuation of the ribbons, and a reliable Al-Cu reflective film that provided protection against a high-power laser. No degradation in characteristics of the GxL device is observed after operating a 5,000- lumen projector for 2,000 hours and conducting 2,000 temperature cycling tests at $-20^{\circ}C$ and $+80^{\circ}C$. At the 2005 World Exposition in Aichi, Japan the world's largest laser projection screen with a size of 2005 inches (10 m ${\times}$ 50 m) and 6 million pixels (1,080 ${\times}$ 5,760) was demonstrated.