• Journal of the Korea Institute of Building Construction
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• v.22 no.2
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• pp.171-182
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• 2022

The regular assessment of a building is important to understand structural safety and latent risk in the early stages of building life cycle. However, methods of traditional assessment are subjective, atypical, labor-intensive, and time-consuming and as such the reliability of these results has been questioned. This study proposed a method to bring accurate results using a 3D laser scanner and integrate them in Building Information Modeling (BIM) to visualize defective condition. The specific process for this study was as follows: (1) semi-automated data acquisition using 3D laser scanner and python script, (2) scan-to-BIM process, (3) integrating and visualizing defective conditions data using dynamo. The method proposed in this study improved efficiency and productivity in a building assessment through omitting the additional process of measurement and documentation. The visualized 3D model allows building facility managers to make more effective decisions. Ultimately, this is expected to improve the efficiency of building maintenance works.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.71-78
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• 2013

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

• Journal of the Korean Institute of Traditional Landscape Architecture
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• v.36 no.4
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• pp.105-112
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• 2018

This study aims to apply 3D scanning technology to the field of landscape planning design. Through this, 3D scans were conducted on Soswaewon Garden and Seongrakwon Gardens to find directions for traditional landscape planning and designs. The results as follows. First, the actual measurement of the traditional garden through a 3D scan confirmed that a precise three-dimensional modeling of ${\pm}3-5mm$ error was constructed through the merging of coordinate values based on point data acquired at each observation point and postprocessing. Second, as a result of the 3D survey, the Soswaewon Garden obtained survey data on Jewoldang House, Gwangpunggak Pavilion, the surrounding wall, stone axis, and Aeyangdan wall, while the Seongnakwon Garden obtained survey data on the topography, rocks and waterways around the Yeongbyeokji pond area. The above data have the advantage of being able to monitor the changing appearance of the garden. Third, spatial information developed through 3D scans could be developed with a three-dimensional drawing preparation and inspection tool that included precise real-world data, and this process ensured the economic feasibility of time and manpower in the actual survey and investigation of landscaping space. In addition, modelling with a three-dimensional 1:1 scale is expected to be highly efficient in that reliable spatial data can be maintained and reprocessed to a specific size depending on the size of the design. In addition, from a long-term perspective, the deployment of 3D scan data is easy to predict and simulate changes in traditional landscaping space over time.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.855-858
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• 1998

본 연구에서는 MML(merged memory logic)구조를 갖는 스캔라인 컨버터를 설계하여 제안한다. 비월주사 방식인 TV 비디오 신호를 FIFO 메모리에 저장하여 순차주사방식인 VGA 비디오 시모호 변환하는 주사선 변환기를 MML 개념으로 설계하였다. MML 회로는 VHDL로 설계하여 V-system으로 시뮬레이션을 수행하고 altera FPGA에 구현한 후, TV 비디오 신호를 PC 모니터로 보기 위한 외장형 tV 수신 시스템에 적용하여 성능을 검증했다. MML 개념으로 설계된 컨버터는 system-on-a-chip 설계의 첫 단계로 메모리와 로직부분으로 구성된 일반적인 컨버터보다 효율적인 시스템 설계를 할 수 있다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.871-872
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• 2008

The method and results of the software implementation of a echo processor for medical ultrasound imaging using a GPU (NVIDIA G80) is presented. The echo signal processing functions are modified in a SIMD manner suitable for the GPU's massively parallel processing architecture so that the GPU's 128 ALUs are utilized nearly 100%. The preliminary result for a frame of image composed of 128 scan lines, each having 10240 16-bit samples, shows that the echo processor can be inplemented at a high rate of 30 frames per second when implemented in C, which is close to the optimized assembly codes running on the TI's TMS320C6416 DSP.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.29-36
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• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.46-52
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• 2009

A Multi-Core/Multi-Thread architecture is adopted for the Shader processor to enhance the processing performance. The Shader processor is designed to utilize its processing core IP for multiple purposes, such as Vertex-Shading, Rasterization, Pixel-Shading, etc. In this paper, we propose a 'Rasterization based on Vector Algorithm' that makes parallel pixels processing possible with Multi-Core and Multi-Thread architecture on the Shader Core. The proposed algorithm takes only 2% operation counts of the Scan-Line Algorithm and processes pixels independently.

• Journal of Digital Contents Society
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• v.18 no.3
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• pp.613-619
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• 2017

This paper presents a CUDA (Compute Unified Device Architecture) code to achieve correct GPU parallel segmented prefix operation results with less than 32 segment length for large data arrays. Mark Harris and Michael Garland had published CUDA code to address the tasks. This paper shows that their code does not generate correct results when the local segment length is less than 32, discusses the cause of the problem, and presents a CUDA code that generates correct results. The segmented parallel prefix operation presented in this paper can be applied as a building block to various large parallel processing algorithms including the k-nearest neighbor search problems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.38-43
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• 2006

In this paper, we propose the efficient dead pixel detection algorithm for CMOS image sensors and its hardware architecture. The CMOS image sensors as image input devices are becoming popular due to the demand for miniaturized, low-power and cost-effective imaging systems. However, the presence of the dead pixels degrade the image quality. To detect the dead pixels, the proposed algorithm is composed of scan, trace and detection step. The experimental results showed that it could detect 99.99% of dead pixels. It was designed in a hardware description language and total logic gate count is 3.2k using 0.25 CMOS standard cell library.

• Journal of architectural history
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• v.26 no.1
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• pp.61-70
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• 2017

We surveyed Preah Pithu monument group site in Angkor. We made the map of present condition throughout the actual measurement and 3D scan. And we restored the floor plan, and completed the map of site placement. During this processing, we confirmed the middle axis of temples and studied the relation of temples and made clear the order of sites. Throughout this studying, we verified the middle axis of sites is not matched in Preah Pithu monument group. It is different aspect comparing with general Khmer religion architectures which were built with the planification belonging to strong royal authority and shared main axis through whole sites. In other words, we can estimate that Preah Pithu monument group was not built with planification rather than expanded as occasional demand during the process of actual use.