• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.9A
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• pp.2325-2332
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• 1998

In this paper, the quality scalable coding of selected region is presented. If a region is semantically more important than the others, it is appropriate that the image compression shcem is capable of handling the regional semantic difference because the information loss of the region of interest is more severe. We propose the quality scalable coding with its model by interoducing the quality scale parameter. It is more extended and generalized image compression philosophy than te conventional coding. As an implementation of the proposed quality scalable coding, H.263 based scheme is presented. This scheme can control the temporal and spatial quality efficiently, and improve the reconstructed image quality of the region of interest.

• ETRI Journal
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• v.28 no.2
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• pp.239-242
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• 2006

In this letter, we propose a new functionality to scalable video coding (SVC), that is, the support of multiple region of interests (ROIs) for heterogeneous display resolution. The main objective of SVC is to provide temporal, spatial, and quality scalability of an encoded bitstream. The ROI is an area that is semantically important to a particular user, especially users with heterogeneous display resolutions. Less transmission bandwidth is needed compared to when the entire region is transmitted/decoded and then sub-sampled or cropped. To support multiple ROIs in SVC, we adopt flexible macroblock ordering (FMO), a tool defined in H.264, and based on it, we propose a way to encode and, independently, decode ROIs. The proposed method is implemented on the joint scalable video model (JSVM) and its functionality verified.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.573-574
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• 2006

A low-power power-aware scalable pipelined Booth recoded multiply & Accumulate unit (PA-MAC) detects the input operands for their dynamic range and accordingly implements a 16-bit, 8-bit or 4-bit multiplication and accumulation operation. The multiplication mode is determined by the dynamic - range detection unit. For the computations, although an area of the proposed PA-MAC is lager than a non-scalable MAC respectively, the proposed PA-MAC proves to be globally more power efficient than a non-scalable MAC.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.1
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• pp.35-41
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• 2009

The H.264/SVC enables network-adaptive video transmission to smart device which uses wireless network. But, quality scalability of H.264/SVC does not consider personal subjective image quality. In addition, its network efficiency also does not optimized because it uses MGS(Medium Grained Scalability) and CGS(Coarse Grained Scalability). Thus, this paper proposed a new scalable ROI algorithm for not only subjective image quality improvement but also network adaptation. To experiment our proposed a scheme, we added designed algorithm to JSVM(Joint Scalable Video Model) open source video codec of H.264/SVC. Experiment was performed according to the pre-defined scenario for simulating various network conditions. Finally, experimental result showed our proposed scalable ROI scheme. It is better than traditional non-selective scheme in subjective video quality.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.11a
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• pp.211-213
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• 2014

최근 4K 이상의 초고해상도 동영상 콘텐츠가 제작되고 있고 그에 따라 많은 기업이 UHD TV 제품을 제작 판매 하고 있다. 따라서 이에 대응할 수 있는 새로운 코덱이 필요하고 그를 위해 HEVC가 개발되었다. 그러나 아직 HEVC의 부호화 효율을 위한 scalable 부호화 방식이 개발 중이다. 초고해상도 비디오 콘텐츠를 다양한 단말기에서 사용할 수 있도록 하기 위해서는 scalable 부호화 방식이 연구개발 되어야 한다. 본 논문에서는 HEVC 이전 버전 코덱인 H.264/AVC를 기반으로 한 scalable 부호화 방식 중 공간적 scalability에 대해 설명하고 여러 방법으로 간단하게 적용시켜 scalable 부호화 방식의 효율의 성능을 예측 평가해 본다. 이 방식은 dowm-sampling한 영상을 HEVC로 부호화하고 이를 up-sampling한 영상과 원영상의 차영상을 HEVC로 부호화하여 전송하는 방식이다. 여기서는 이 방식의 결과를 토대로 이 방식의 문제점을 지적하고 이를 토대로 한 향후의 연구방향을 제시한다.

• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.101-108
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• 2019

In this paper, we propose a new scalable and reliable combat system software in battleship which was developed procedurally in the past. Recently, combat system software is required to change frequently due to addition of new equipment and change of function. To solve those problems, this paper propose how to change combat system software into scalable software using class structure change and design pattern. Simulation results show that our scheme provides better performances and reliability than conventional scheme. Therefore proposed scheme can be efficiently used in Naval combat system.

• International Journal of Advanced Culture Technology
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• v.11 no.1
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• pp.290-295
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• 2023

The global warming by greenhouse gases causes climate change and disasters such as earthquakes and tsunamis frequently, leading to great damage. It is important to build efficient and scalable disaster response services to minimize the damage. Existing disaster warning service by the mobile text is limited by the scalability and the data size to be delivered. In this paper, we propose a framework for disaster response services that is efficient and flexible by allowing to adopt various indexing schemes and scalable by supporting any number of clients in disaster situations anytime and anywhere. Also, the framework by wireless data broadcast can be free from the limitation of the size of data to be delivered. We design and implement the proposed framework and evaluate the framework. For the evaluation, we simulate the implemented framework by adopting various indexing schemes like HCI, DSI and TTSI, and by comparing the access times of the clients. Through the evaluation, we show that the proposed framework can provide efficient and scalable and flexible disaster response services.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.1
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• pp.94-101
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• 2009

This paper presents scalable modeling of spiral inductors for RFIC design based on $0.13{\mu}m$ RF CMOS process. For scalable modeling, several inductor patterns are designed and fabricated with variations of width, number of turns and inner radius. Feeding structures are optimized for accurate de-embedding of pad effects. After measuring the S parameters of the fabricated patterns, double-$\pi$ equivalent circuit parameters are extracted for each device and their geometrical dependences are modeled as scalable functions. The inductor library provides two types of models including standard and symmetric inductors. Standard and symmetric inductors have the range of $0.12{\sim}10.7nH$ and $0.08{\sim}13.6nH$ respectively. The models are valid up to 30GHz or self-resonance frequency. Through this research, a scalable inductor library with an error rate below 10% is developed for $0.13{\mu}m$ RF CMOS process.

• Journal of Broadcast Engineering
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• v.20 no.4
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• pp.497-508
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• 2015

Current communication networks consist of channels with various throughputs, protocols, and packet loss rates. Moreover, there are also diverse user multimedia consumption devices having different capabilities and screen sizes. Thus, a practical necessity of scalability on video coding have been gradually increasing. Recently, The Scalable High Efficiency Video Coding(SHVC) standard is developed by Joint Collaborative Team on Video Coding(JCT-VC) organized in cooperation with MPEG of ISO/IEC and VCEG of ITU-T. This paper introduces coding tools of SHVC including adopted and unadopted tools discussed in the process of the SHVC standardization. Furthermore, the individual tool and combined tool set are evaluated in terms of coding efficiency relative to a single layer coding structure. This analysis would be useful for developing a fast SHVC encoder as well as researching on a new scalable coding tool.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.8
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• pp.1095-1102
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• 2021

A scalable ECC architecture with high scalability and flexibility between performance and hardware complexity is proposed. For architectural scalability, a modular arithmetic unit based on a one-dimensional array of processing element (PE) that performs finite field operations on 32-bit words in parallel was implemented, and the number of PEs used can be determined in the range of 1 to 8 for circuit synthesis. A scalable algorithms for word-based Montgomery multiplication and Montgomery inversion were adopted. As a result of implementing scalable ECC processor (sECCP) using 180-nm CMOS technology, it was implemented with 100 kGEs and 8.8 kbits of RAM when N_PE=1, and with 203 kGEs and 12.8 kbits of RAM when N_PE=8. The performance of sECCP with N_PE=1 and N_PE=8 was analyzed to be 110 PSMs/sec and 610 PSMs/sec, respectively, on P256R elliptic curve when operating at 100 MHz clock.