• Environmental and Resource Economics Review
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• v.31 no.4
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• pp.849-864
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• 2022

In case of a specific sector being divided into sub-sectors, this study presents a process for estimating an input-output table, which is frequently used as basic data in fields of energy and environment economics. RAS method, which is universally used for this case, requires information on production, intermediate input sum, and intermediate demand sum for each sector in the new table. But in many cases, it is difficult to secure information on intermediate demand sum by sector. This study suggests a process for estimating a new input-output table without using information of intermediate demand sum in the case of sector separation, under the assumption that information of production value and intermediate input sum by sector are available. The key idea is that the values of many elements in the input-output table after disaggregation are the same as those in the table before disaggregation and that the sum of the elements after disaggregation, equals the values of the elements before disaggregation. The process of estimating the intemediate transaction matrix or the input coefficient matrix is presented by using these information instead of intermediate demand sum information. A small-scale simulation shows that the average error rate of the process proposed in this study is about 11.23% in estimating input coefficients, which is smaller than the 11.30% estimation error of RAS using the information of intermediate demand sum. However, since it is known in the literature that using additional information does not always improve estimation performance compared to not using it, additional research on various simulations is needed to apply the method of this study to reality.

• Electronics and Telecommunications Trends
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• v.39 no.1
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• pp.62-73
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• 2024

Artificial intelligence relies on data-driven analysis, and the data processing performance strongly depends on factors such as memory capacity, bandwidth, and latency. Fast and large-capacity memory can be achieved by composing numerous high-performance memory units connected via high-performance interconnects, such as Compute Express Link (CXL). CXL is designed to enable efficient communication between central processing units, memory, accelerators, storage, and other computing resources. By adopting CXL, a composable computing architecture can be implemented, enabling flexible server resource configuration using a pool of computing resources. Thus, manufacturers are actively developing hardware and software solutions to support CXL. We present a survey of the latest software for CXL memory utilization and the most recent CXL memory emulation software. The former supports efficient use of CXL memory, and the latter offers a development environment that allows developers to optimize their software for the hardware architecture before commercial release of CXL memory devices. Furthermore, we review key technologies for improving the performance of both the CXL memory pool and CXL-based composable computing architecture along with various use cases.

• International journal of advanced smart convergence
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• v.9 no.3
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• pp.253-259
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• 2020

Most of today's large-scale cloud systems and enterprise data centers are distributing resources to improve scalability and resource utilization. NVMe-over-Fabric protocol allows submitting NVMe commands to a remote NVMe SSD through RDMA (Remote Direct Memory Access) network. It is attracting attention recently because it is possible to construct a disaggregation storage system with low latency through the protocol. However, the current I/O stack of NVMe-over-Fabric has an inefficient structure for maintaining compatibility with the traditional I/O stack. Therefore, in this paper, we propose a new mechanism to reduce I/O latency and CPU overhead by modifying I/O path of NVMe-over-Fabric to pass through legacy block layer. According to the performance evaluation results, the proposed mechanism is able to reduce the I/O latency and CPU overhead by up to 22% and 24% compared to the existing NVMe-over-Fabrics protocol, respectively.

• ETRI Journal
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• v.44 no.6
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• pp.1020-1033
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• 2022

In this paper, we propose novel disaggregated memory module (dMM) architecture and memory access control schemes to solve the collision and contention problems of memory disaggregation, reducing the average memory access time to less than 1 ㎲. In the schemes, the distributed scheduler in each dMM determines the order of memory read/write access based on delay-sensitive priority requests in the disaggregated memory access frame (dMAF). We used the memory-intensive first (MIF) algorithm and priority-based MIF (p-MIF) algorithm that prioritize delay-sensitive and/or memory-intensive (MI) traffic over CPU-intensive (CI) traffic. We evaluated the performance of the proposed schemes through simulation using OPNET and hardware implementation. Our results showed that when the offered load was below 0.7 and the payload of dMAF was 256 bytes, the average round trip time (RTT) was the lowest, ~0.676 ㎲. The dMM scheduling algorithms, MIF and p-MIF, achieved delay less than 1 ㎲ for all MI traffic with less than 10% of transmission overhead.