• JSTS:Journal of Semiconductor Technology and Science
• /
• 제3권2호
• /
• pp.83-88
• /
• 2003

The reset operation of a CCD image sensor was improved using charge trapping of a MOS structure to realize a loe voltage driving. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2V to 5.5V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with $492(H){\;}{\times}{\;}510(V)$ pixels adopting this structure showed complete reset operation with the driving voltage of 3.0V. The resolution chart taken with the image sensor shows no image flow to the illumination of 30 lux, even in the driving voltage of 3.0V.

• 한국지능시스템학회:학술대회논문집
• /
• 한국퍼지및지능시스템학회 1998년도 추계학술대회 학술발표 논문집
• /
• pp.568-576
• /
• 1998

In this thesis discuss with a flexible robotic finger design and controller which is used for the micro flexible robotic finger. So, miniaturization, precision, controller for the control of grasping force and actuator were needed. And, even if we develop a new actuator and controller, in order to use on real system, we must considerate of a many side problem. In a force control of micro flexible finger for grasping an object, the fingertip's vibration was more important task of accuracy control. And, controller were adopt the PD/PI mixed type fuzzy controller. The controller were consist of two part, one is a PD type fuzzy controller for increase the rising time response, the other is a PI type fuzzy controller for decrease of steady-state error. Especially, in a PD type fuzzy controller, we used only seven rules. And, for a PI controller, we adopt a reset factor for the control of input values. so, we have overcome the exceed of controller's input range. For the estimate of ontroller's utility and usefulness, we have experiment and computer simulation of three cases. First, we consider of unit force grasping control for a task object, which is 0.03N. Second, bounding grasping force control which is add to a sinusoidal force on the unit force. At this cases the task force is (0.03+0.01 sin wt N). And consider of following of rectangular forces.

• 대한전자공학회논문지
• /
• 제22권1호
• /
• pp.68-74
• /
• 1985

이 논문에서는 standard cell의 layout을 위한 doglegging을 하지 않는 channel 배선 시스템에 대하여 서술할 것이다. 이 시스템은 주어진 net list specification을 만족시키기 위하여, 각각 standard cell 의 직선 배열 결합인 두 row 사이의 구평 track에서 이층의 최종 배선 패턴을 만들어 준다. 이 논문에서 사용한 CMOS cell library는 9개의 기본 cell을 가지고 있으며, Mead-Cogway 방식에서의 A-2micron을 사용하여 CIF(Caltech Intermediate From) 형태로 표현되었다. Component library에는 각 cell 내의 pin들의 이름. 위치 및 layer type 등의 입출력 port 특성이 저장되어서, CROUT라는 channel routing program에서 입력 자료로 사용된다. 또 다른 program NETPLOT은 routing 결과를 개략적으로 도시하여 주며, NETCIF에서는 최종의 자세한 layout을 CIF file로 만들어 주고 있다. 기본 cell을 이온하여 set/reset이 있는 dynamic Raster-slave형 D flip-flop에 대한 channel routing의 경우 VAX l1/780 에서 4초의 CPU 시간이 소요되었다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
• /
• pp.47-50
• /
• 2002

An extended-counting analog to digital converter (ADC) is designed to have a high resolution(14bit) with low power consumption and small dia area. First order sigma-delta modulator with a simple counter for incremental operation eliminates the need of big decimation filter in conventional sigma-delta type ADC. To improve the accuracy and linearity, extended mode of successive approximation is followed. For 14-bit conversion operation, total 263 clocks(1 clock for reset, 256 clocks for incremental operation and extended 6 clocks for successive approximation operation) are needed with the sampling rate of 10 Ms/s This ADC is implemented in a 0.6um standard CMOS technology with a die area of 1 mm ${\times}$ 0.75 mm.

• 제어로봇시스템학회논문지
• /
• 제17권1호
• /
• pp.54-60
• /
• 2011

The flight control law designed for prototype aircraft often leads to degraded stability and performance, although developed control law verify by non-real time simulation and pilot based evaluations. Therefore, the proper evaluation methods should be applied such that flight control law designed can be verified in real flight environment. The one proposed in this paper is IFS (In-Flight Simulator). Currently, this system has been implemented into the F-18 HARV (High Angle of Attack Research Vehicle), SU-27 and F-16 VISTA (Variable stability In flight Simulation Test Aircraft) programs. The IFS necessary switching control law such as fader logic and integrator stand-by mode to reduce abrupt transient and minimize the integrator effect for each flight control laws switching. This paper addresses the concept of switching mechanism with fader logic of "TFS (Transient Free Switch)" and stand-by mode of "feedback type" based on SSWM (Software Switching Mechanism). And the result of real-time pilot evaluation reveals that the aircraft is stable for inter-conversion of flight control laws and transient response is minimized.

• 센서학회지
• /
• 제15권2호
• /
• pp.112-119
• /
• 2006

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with $128{\times}128$ pixel array has been designed and fabricated by using $0.35{\mu}m$ 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.

• 제어로봇시스템학회논문지
• /
• 제13권7호
• /
• pp.694-702
• /
• 2007

The SSWM(Software Switching Mechanism) of I-processor concept using non-real time in-house software simulation program is an effective method in order to develop the flight control law in desktop or HQS environment. And, this system has some advantages compare to HSWM(Hardware Switching Mechanism) such as remove the time delay effectiveness and reduce the costs of development. But, if this system loading to the OFP(Operational Flight Program), the OFP guarantee the enough throughput in order to calculate the two control law at once. Therefore, the HSWM(Hardware Switching Mechanism) of 2-processor concept is necessary. This paper addresses the concept of HSWM of the HQS-PC interface using TCP/IP(Transmission Control Protocol/Internet Protocol) communication based on flight control law of advanced supersonic trainer. And, the fader logic of TFS(Transient Free Switch) and stand-by mode of reset '0' type are designed in order to reduce the abrupt transient response and minimize the integrator effect in pitch axis. The result of the analysis based on HQS pilot simulation using HSWM reveals that the flight control systems are switching between two computers without any problem.

• 센서학회지
• /
• 제16권6호
• /
• pp.475-483
• /
• 2007

This paper proposes a readout integrated circuit (ROIC) for $32{\times}32$ infrared focal plane array (IRFPA) detector, which consist of reference resistor, detector resistor, reset switch, integrated capacitor and operational amplifier. Proposed ROIC is designed using $0.35{\;}{\mu}m$ 2P-4M (double poly four metal) n-well CMOS process parameters. Low noise folded cascode operational amplifier which is a key element in the ROIC showed 12.8 MHz unity-gain bandwidth and open-gain 89 dB, phase margin $67^{\circ}$, SNR 82 dB. From proposed circuit, we gained output voltage variation ${\Delta}17{\};mV/^{\circ}C$ when the detector resistor varied according to the temperature.

• 항공우주시스템공학회지
• /
• 제9권1호
• /
• pp.12-18
• /
• 2015

The inter-conversion between different control laws in flight has a lot of risk. The SWM(Switching Mechanism) including logic and stand-by mode is designed to analyze the transient response of aircraft during inter-conversion between different control laws, based on the in-house software for non-real-time and real-time simulation. The SWM applies the fader logic of TFS(Transient Free Switch) to minimize the transient response of an aircraft during the inter-conversion, and applies the reset '0' type of the stand-by mode to prevent surface saturation due to integrator effect in the disengaged flight control law. The transition time is also important to minimize the objectionable transient response in the inter-conversion, as well as the transition control law design. This paper addresses the results of non-real-time simulation for the characteristics of transient response to different transition time to select the adequate transient time, and the real-time pilot evaluation, using SSWM(Software Switching Mechanism) and HSWM(Hardware Switching Mechanism), which is met for Level 1 flying qualities and assures safety of flight.

• Transactions on Electrical and Electronic Materials
• /
• 제11권1호
• /
• pp.20-23
• /
• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.