• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.6
• /
• pp.615-628
• /
• 2015

CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture can be considered as a suitable solution for the fault-tolerant computing. However, there have been a few research projects based on fault-tolerant CGRA without exploiting the strengths of CGRA as well as their works are limited to single CGRA. Therefore, in this paper, we propose two approaches to enable exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. One is a resilient inter-CGRA fabric that is ring-based sharing fabric (RSF) with minimal interconnection overhead. Another is a novel intra/inter-CGRA reconfiguration technique on RSF for maximizing utilization of the resources when faults occur. Experimental results show that the proposed approaches achieve up to 94% faulty recoverability with reducing area/delay/power by up to 15%/28.6%/31% when compared with completely connected fabric (CCF).

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.4
• /
• pp.405-414
• /
• 2016

IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).

• ETRI Journal
• /
• v.38 no.1
• /
• pp.100-111
• /
• 2016

This paper presents a low-complexity channel-adaptive reconfigurable $4{\times}4$ QR-decomposition and M-algorithm-based maximum likelihood detection (QRM-MLD) multiple-input and multiple-output (MIMO) detector. Two novel design approaches for low-power QRM-MLD hardware are proposed in this work. First, an approximate survivor metric (ASM) generation technique is presented to achieve considerable computational complexity reduction with minor BER degradation. A reconfigurable QRM-MLD MIMO detector (where the M-value represents the number of survival branches in a stage) for dynamically adapting to time-varying channels is also proposed in this work. The proposed reconfigurable QRM-MLD MIMO detector is implemented using a Samsung 65 nm CMOS process. The experimental results show that our ASM-based QRM-MLD MIMO detector shows a maximum throughput of 288 Mbps with a normalized power efficiency of 10.18 Mbps/mW in the case of $4{\times}4$ MIMO with 64-QAM. Under time-varying channel conditions, the proposed reconfigurable MIMO detector also achieves average power savings of up to 35% while maintaining a required BER performance.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.174-181
• /
• 2004

In this paper, we review the four receiver architectures and four methods for multi-standard receiver design. Propose reconfigurable RF block can be used for both low-IF and direct conversion architecture. Also, using reconfigurable mixer method, it can be operated at $2{\sim}6$ GHz range for multi-standard receiver. It consists of wideband mixer, filter, and automatic gain control amplifier and to get wide-band operation, $2{\sim}6$ GHz, wide-band mixer use flexible input matching method. Besides, to design multi-standard receiver, LNA bank that support each standard is necessary and it has good performance to compensate the performance of wide-band mixer. Finally, we design and simulate proposed reconfigurable RF block and to prove that it has acceptable performances for various wireless standards, the LNA bank that supports both IEEE 802.11a/b/g and WCDMA is also designed and simulated with it.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.531-532
• /
• 2006

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.7 s.349
• /
• pp.38-49
• /
• 2006

In this paper, a novel concept based on embedded processor and reconfigurable logic is proposed for efficient manufacturing test and design verification. Unlike traditional gap between design verification and manufacturing test, proposed concept is to combine both design verification and manufacturing test. The semiconductor chip which is using the proposed concept is named "SwToC" and SwToC stands for System with Test On a Chip. SwToC has two main features. First, it has functional verification function on a chip and this function could be made by using embedded processor, reconfigurable logic and memory. Second, it has internal ATE on a chip and this feature also could be made by the same architecture. To evaluate the proposed SwToC, we have implemented SwToC using commercial FPGA device with embedded processor. Experimental results showed that the proposed chip is possible for real application and could have faster verification time than traditional simulation method. Moreover, test could be done using low cost ATE.

• Journal of Broadcast Engineering
• /
• v.20 no.6
• /
• pp.963-966
• /
• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.

• Journal of Internet Computing and Services
• /
• v.7 no.2
• /
• pp.121-136
• /
• 2006

Software architecture and protocols to be maintained between components for the reconfigurable SDR system is analyzed and suggest system design idea for the implementation of software. To do this, related surveys are reviews and set up the system model with the structure of embedded system. SDR system architecture is suggested with five layered structure, consisted with hardware, operating system, middle-ware, service objects and application layer. SDR system is designed to be work on the basis of Linux operating system, and aimed to be scalable and reconfigurable. It is introduced the design result of software protocol and state transition diagram for the implementations of software download function which is the most important feature in SDR.

• Advances in Computational Design
• /
• v.7 no.3
• /
• pp.189-210
• /
• 2022

Deployable structures have the ability to shift from a compact state to an expanded functional configuration. By extension, reconfigurability is another function that relies on embedded computation and actuators. Linkage-based mechanisms constitute promising systems in the development of deployable and reconfigurable structures with high flexibility and controllability. The present paper investigates the deployment and reconfigurability of modular linkage structures with a pin and a sliding support, the latter connected to a linear motion actuator. An appropriate control sequence consists of stepwise reconfigurations that involve the selective releasing of one intermediate joint in each closed-loop linkage, effectively reducing it to a 1-DOF "effective crank-slider" mechanism. This approach enables low self-weight and reduced energy consumption. A kinematics and finite-element analysis of different linkage systems, in all intermediate reconfiguration steps of a sequence, have been conducted for different lengths and geometrical characteristics of the members, as well as different actuation methods, i.e., direct and cable-driven actuation. The study provides insight into the impact of various structural typological and geometrical factors on the systems' behavior.

• Proceedings of the Korean Information Science Society Conference
• /
• 2005.11a
• /
• pp.355-357
• /
• 2005

This paper describes the architecture and modeling of adaptive and reconfigurable OS in wireless distributed sensor networks. Before initial sensor nodes are deployed in a sensor field, minimum functions including basic OS and routing algorithms are required for these nodes to send request messages for dynamic reconfigurations and receive response messages from a task manager. When the downloading is finished, each sensor node can reconfigure the initial state and be ready to start its functions. By applying this reconfigurable modeling, sensor nodes can be easily deployed in the sensor field and dynamically programmed during a bootstrap process.