• 제어로봇시스템학회:학술대회논문집
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• 1987.10a
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• pp.770-775
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• 1987

In this paper, design and development experiences of a vision based robotic assembly system for electronic components are described. Specifically, the overall system consists of the following three subsystems each of which employs a 16 bit Preprocessor MC 68000 : supervisory controller, real-time vision system, and servo system. The three microprocessors are interconnected using the time shared common memory bus structure with hardwired bus arbitration scheme and operated as a master-slave type in which each slave is functionally fixed in view of software. With this system architecture, the followings are developed and implemented in this research; (i) the system programming language, called 'CLRC', for man-machine interface including the robot motion and vision primitives, (ii) real-time vision system using hardwired chain coder, (iii) the high-precision servo techniques for high speed de motors and high speed stepping motors. The proposed control system were implemented and tested in real-time successfully.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.1
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• pp.39-42
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• 2002

For the purpose of modeling EEG signal which has nonstationary and nonlinear dynamic characteristics, this paper propose a state feedback real time recurrent neural network model. The state feedback real time recurrent neural network is structured to have memory structure in the state of hidden layers so that it has arbitrary dynamics and ability to deal with time-varying input through its own temporal operation. For the model test, Mackey-Glass time series is used as a nonlinear dynamic system and the model is applied to the prediction of three types of EEG, alpha wave, beta wave and epileptic EEG. Experimental results show that the performance of the proposed model is better than that of other neural network models which are compared in this paper in some view points of the converging speed in learning stage and normalized mean square error for the test data set.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.8
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• pp.1217-1226
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• 1989

This paper describes a design of hardware system for real time automatic diagnosis of ECG arrhythmia based on pipeline processor consisting of three microcomputer. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters-heart rate, morpholigy, axis, and ST segment-are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. Therefore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory unit is designed to decrease the delay time caused by data transfer between processors and be which the delay time can be taken 1% of one clock period.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.944-953
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• 1990

This paper describes design and implementation of a real-time high-precision vision system for an automation of SMT(surface mounting technology ). Also, a part inspection algorithm which calculates the position and direction of SMD(surface mounted device) accurately and performs the ruling using those information are presented, and a parallel processing technique for implementing those algorithms is also described. For a real-time implementation of iage acquisition and processing, several hardware modules, namely, multi-functional A/D-D/A board, frame memory board are developed. Particularly, a PE (processing element) board which employs the DSP56001 DSP (digital signal processor) is developed for the purpose of concurrent processing of part inspection algorithms. A stand-alone vision system is built by integration of the developed hardware modules and related softwares.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.27-33
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• 1993

This paper describes the hardware implementation of 2-D FIR digital filter for a real-time image processing. Generally, the most time-consuming operation in signal processing is the multiplication operation. To avoid it in digital filter. Pelid and Liu proposed the distributed arithmetic method for the one-dimensional case. The implementation method proposed in this paper is to extend Pelid's method to two-dimensional FIR filter using simple ROM lookup table and to use the technique of pipe lining two main operations of memory access and arithmetic. As a result, the speed of our proposed hardware implementation is two times faster than that of conventional methods and can be close to the real time speed.

• Journal of Computing Science and Engineering
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• v.6 no.1
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• pp.26-38
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• 2012

Java has been increasingly used in programming for real-time systems. However, some of Java's features such as automatic memory management and dynamic compilation are harmful to time predictability. If these problems are not solved properly then it can fundamentally limit the usage of Java for real-time systems, especially for hard real-time systems that require very high time predictability. In this paper, we propose to exploit multicore computing in order to reduce the timing unpredictability that is caused by dynamic compilation and adaptive optimization. Our goal is to retain high performance comparable to that of traditional dynamic compilation, while at the same time, obtain better time predictability for Java virtual machine (JVM). We have studied pre-compilation techniques to utilize another core more efficiently, preoptimization on another core (PoAC) scheme to replace the adaptive optimization system (AOS) in Jikes JVM and the counter based optimization (CBO). Our evaluation reveals that the proposed approaches are able to attain high performance while greatly reducing the variation of the execution time for Java applications.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.731-733
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• 1988

This paper describes a design of hardware system for real time automatic diagnosis of ECG arrhythmia based on pipeline processor consisting of the three microcomputer. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters - heart rate, morphology, axis, and ST segment - are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. There-fore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and by which the delay time can be taken 1 % of one clock period.

• Information and Communications Magazine
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• v.10 no.10
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• pp.22-29
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• 1993

This paper describes development of a real-time voice recognition dialing system which can recognize around one hundred word vocabularies in speaker independent mode. The voice recognition algorithm is implemented on a DSP board with a telephone interface plugged in an IBM PC AT/486. In the DSP board, procedures for feature extraction, vector quantization(VQ), and end-point detection are performed simultaneously in every 10msec frame interval to satisfy real-time constraints after the word starting point detection. In addition, we optimize the VQ codebook size and the end-point detection procedure to reduce recognition time and memory requirement. The demonstration system is being displayed in MOBILAB of Korea Mobile Telecom at the Taejon EXPO '93.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.194-199
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• 2003

Depth error correction effect for maladjusted stereo cameras with calibrated pixel distance parameter is presented. The proposed neural network technique is the real time computation method based theory of inter-node diffusion for searching the safety distances from the sudden appearance-objects during the work driving. The main steps of the distance computation using the theory of stereo vision like the eyes of man is following steps. One is the processing for finding the corresponding points of stereo images and the other is the interpolation processing of full image data from nonlinear image data of objects. All of them request much memory space and time. Therefore the most reliable neural-network algorithm is derived for real-time matching of objects, which is composed of a dynamic programming algorithm based on sequence matching techniques.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.3
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.