• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1460-1468
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• 2000

The goal of this research is the real-time implementation of MPEG-1 Layer III audio decoder using the fixed-point digital signal processor of TMS320C6201 The main job for this work is twofold: one is to convert floating-point operation in the decoder into fixed-point operation while maintaining the high resolution, and the other is to optimize the program to make it run in real-time with memory size as small as possible. We, especially, devote much time to the descaling module in the decoder for conversion of floating-point operation into fixed-point operation with high accuracy. The inverse modified cosine transform(IMDCT) and synthesis polyphase filter bank modules are optimized in order to reduce the amount of computation and memory size. After the optimization process, in this paper, the implemented decoder uses about 26% of maximum computation capacity of TMS320C6201. The program memory, data ROM, data RAM used in the decoder are about 6.77kwords, 3.13 kwords and 9.94 kwords, respectively. Comparing the PCM output of fixed-point computation with that of floating-point computation, we achieve the signal-to-noise ratio of more than 60 dB. A real-time operation is demonstrated on the PC using the sound I/O and host communication functions in the EVM board.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• Journal of Korea Spatial Information System Society
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• v.9 no.2
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• pp.13-23
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• 2007

Recently there is growing Interest in LBS(Location Based Service) requiring real-time services and the spatial main memory DBMS for efficient Telematics services. In order to optimize existing disk-based multi-dimensional Indexes of the spatial main memory DBMS in the main memory, multi-dimensional index structures have been proposed, which minimize failures in cache access by reducing the entry size. However, because the reduction of entry size requires compression based on the MBR of the parent node or the removal of redundant MBR, the cost of MBR reconstruction increases in index update and the efficiency of search is lowered in index search. Thus, to reduce the cost of MBR reconstruction, this paper proposed the RSMBR(Relative-Sized MBR) compression technique, which applies the base point of compression differently in case of broad distribution and narrow distribution. In case of broad distribution, compression is made based on the left-bottom point of the extended MBR of the parent node, and in case of narrow distribution, the whole MBR is divided into cells of the same size and compression is made based on the left-bottom point of each cell. In addition, MBR was compressed using a relative coordinate and size to reduce the cost of search in index search. Lastly, we evaluated the performance of the proposed RSMBR compression technique using real data, and proved its superiority.

• Korean Journal of Cognitive Science
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• v.18 no.2
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• pp.113-138
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• 2007

The effects of schema on accurate and false memories of items in a scene were investigated in two experiments: Recognition of items in a scene was tested immediately in Experiment 1 and three days later in Experiment 2. In both experiments, the following three variables were manipulated: Exposure time (250ms or 10000ms), picture mode (completed pictures or scrambled pictures), and manipulation mode (missing item or substituted item). Experiment 1 had yielded three important results: First, although accurate memory for presented items got increased when the exposure time was longer, false memory of the critical lures was not changed. Second, false memory of critical lures in the missing condition, where there was not any conflict between verbatim information and gist information, was higher than that of the substituted condition, where verbatim information of the item that replaced the lure was in conflict with the gist information. Third, accurate memory for atypical items in the substituted rendition, which had replaced the critical lures and in conflict with the schema, was higher than that in the missing condition. In Experiment 2, recognition test were administered 72 hours after the participants saw the picture. The three effects mentioned in Experiment 1 had disappeared in Experiment 2. The results of Experiment 2 might be due to the selective weakening of verbatim information compared to the persistence of the gist (or schematic) information. The results of Experiments 1 and 2 showed that false memory of critical lures is more persistent than the accurate memory of non-critical information. Theoretical implications of the results were considered in terms of the function of the verbatim and gist information.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.11
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• pp.1457-1463
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• 1999

This paper develops an real-time expert system for the electronic interlocking system. it obtains the higher safety by determining the railway interlocking strategy in order to prevent trains from colliding, and derailing in the viewpoint of veteran expert, considering the situation of station in real-time. The expert system determines the real-time interlocking strategy by confirming the interlocking relationships among signal facilities based on the interlocking knowledge base from input information such as signal, points, and it is implemented as the rule-based system in order to represented accurately and effectively the interlocking relationships. Especially in case of emergency the function which determines the rational route coordinating with IIKBAG on the workstation is designed in order to minimize the spreading effect. It is implemented in C computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the build and interface of the station structure database. And, the validity of the built expert system is proved by simulating the diversity cases which may occur in the real system for the typical station model.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.299-310
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• 2001

In this paper, we study the methodology of distributing the requests of clients based on the state of real server in the LVS(Linux virtual server) clustering system. The WLC(weighted least connection) algorithm in the LVS cluster system is studied. The load distributing algorithm which assigns a weight into each real server is devised by considering the load of real servers. The load test is executed to estimate the load of real servers using a load generating tool. Throughout the result of the experiment, we suggest new load distributing algorithm based on the usage of physical memory of each real server. It is shown that the correction potentiality of new algorithm is somewhat better than that of the WLC algorithm.

• Journal of KIISE:Information Networking
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• v.32 no.4
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• pp.443-451
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• 2005

Stateful inspection devices must maintain flow information. These devices create the flow information also for network attack packets, and it can fatally inflate the dynamic memory allocation on stateful inspection devices under network attacks. The memory inflation leads to memory overflow and subsequent performance degradation. In this paper, we present a guideline to set the flow entry timeout for a stateful inspection device to remove harmful embryonic entries created by network attacks. Considering Transmission Control Protocol (TCP) if utilized by most of these attacks as well as legitimate traffic, we propose a parsimonious memory management guideline based on the design of the TCP and the analysis of real-life Internet traces. In particular, we demonstrate that for all practical purposes one should not reserve memory for an embryonic TCP connection with more than (R+T) seconds of inactivity where R=0, 3, 9 and $1\leqq{T}\leqq{2}$ depending on the load level.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.7-13
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• 2002

When a USB digital camera is used for PC video-conference applications, motion picture data need to be transferred to the PC through the USB port. Due to the mismatch between the data rates of the USB and the motion picture, data compression should be performed before the transmission from the USB. While many motion picture compression algorithms require large intermediate memory space, the JPEG algorithm does not need to store an entire frame for the compression. Instead, a relatively small buffer is required at the input of the JPEG compression engine to resolve the inconsistency between the orders of the inputted data and the consumed data. Data reordering can be easily implemented using a double buffering scheme, which still requires a considerable size of memory. In this paper, a novel memory management scheme is proposed to avoid the double buffering. The proposed memory architecture requires a small amount of memory and a simple address generation scheme, resulting in overall cost reduction.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.1
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• pp.19-26
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• 2010

In this paper, we adopt Storage Class Memory, which is next-generation non-volatile RAM technology, as part of main memory parallel to DRAM, and exploit the SCM+DRAM main memory system from the dependability perspective. Our system provides instant system on/off without bootstrapping, dynamic selection of process persistence or non-persistence, and fast recovery from power and/or software failure. The advantages of our system are that it does not cause the problems of checkpointing, i.e., heavy overhead and recovery delay. Furthermore, as the system enables full application transparency, our system is easily applicable to real-world environments. As proof of the concept, we implemented a system based on a commodity Linux kernel 2.6.21 operating system. We verify that the persistence enabled processes continue to execute instantly at system off-on without any state and/or data loss. Therefore, we conclude that our system can improve availability and reliability.

• Journal of the Korean Institute of Intelligent Systems
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• v.13 no.2
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• pp.154-162
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• 2003

In this paper, Associative Memory with Cellular Neural Networks classifies and recognizes image patterns as an operator applied to image process. CNN processes nonlinear data in real-time like neural networks, and made by cell which communicates with each other directly through its neighbor cells as the Cellular Automata does. It is applied to the optimization problem, associative memory, pattern recognition, and computer vision. Image processing with CNN is appropriate to 2-D images, because each cell which corresponds to each pixel in the image is simultaneously processed in parallel. This paper shows the method for designing the structure of associative memory based on CNN and getting output image by choosing the most appropriate weight pattern among the whole learned weight pattern memories. Each template represents weight values between cells and updates them by learning. Hebbian rule is used for learning template weights and LMS algorithm is used for classification.