• Journal of Biomedical Engineering Research
• /
• v.28 no.3
• /
• pp.429-440
• /
• 2007

A coded excitation has been studied to improve the performance for ultrasound imaging in term of SNR, imaging frame rate, contrast to tissue ratio, and so forth. However, it requires a complicated arbitrary waveform transmitter for each active channel that is typically composed of a multi-bit Digital-to-Analog Converter (DAC) and a linear power amplifier (LPA). Not only does the LPA increase the cost and size of a transmitter block, but it consumes much power, increasing the system complexity further and causing a heating-up problem. This paper proposes an optimized 1.5bit fourth order sigma-delta modulation technique applicable to design an efficient arbitrary waveform generator with greatly reduced power dissipation and hardware. The proposed SDM can provide a required SQNR with a low over-sampling ratio of 4. To this end, the loop coefficients are optimized to minimize the quantization noise power in signal band while maintaining system stability. In addition, the decision level for the 1.5 bit quantizer is optimized for a given input waveform, which results in the SQNR improvement of more than 5dB. Computer simulation results show that the SQNR of a FM(frequency modulated) signal generated by using the proposed method is about 26dB, and the peak side-lobe level (PSL) of its compressed waveform on receive is -48dB.

• The Journal of the Acoustical Society of Korea
• /
• v.15 no.5
• /
• pp.107-112
• /
• 1996

In this paper we propose a new fast codebook training algorithm for reducing the searching time of LBG algorithm. For each training data, the proposed algorithm stores the indexes of codewords that are close to that training data in the first iteration. It reduces computation time by searching only those codewords, the indexes of which are stored for each training data. Compared to one of the previous fast training algorithm, FSLBG, it obtains a better codebook with less exccution time. In our experiment, the performance of the codebook generated by the proposed algorithm in terms of peak signal-to-noise ratio(TSNR) is very close to that of LBG algorithm. However, the codewords to be searched for each training data of the proposed algorithm is only about 6%, for a codebook size of 256 and 1.6%, for a codebook size of 1.24, of LBG algorithm.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.3
• /
• pp.21-30
• /
• 1990

This paper describes a hardware implementation of the interframe monochrome video CODEC using a MC-CVQ(Motion Compensated and Classified Vector Quantization) algorithm. The specifications of this CODEC are (1) the resolution of image is $128{\times}128$ pixels, and (2) the transmission rates are about 10frames/sec at the 64Kbps channel. In order to design the CODEC under these conditions, it is implemented by a multiprocessor system composed of MC unit, CVQ nuit and decoder unit, which are controlled by microprogramming technique. And the 3~stage pipelined ALU(Arithmetic and Logic Unit) is adopted to calculate the minimum error distance in the MC unit and CVQ nuit. The realized system shows that the transmission rates are 6-15 frames/sec according to the relative motion of the video signal.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.40 no.2
• /
• pp.11-19
• /
• 2003

This paper proposes an algorithm to reduce the estimation error of surface spectral-reflectance(SR) using a conventional 3-band RGB camera. In the proposed method, estimation error can be reduced by using adaptive principal components(PCs) for each color region. In order to build adaptive set of PCs, n SR populations are organized for n PC sets by using Lloyd quantizer design algorithm. Macbetch ColorCheckcer is utilized as initial representative SR values for 1485 Munsell color chips of total color population and the Munsell chips arc divided subsets and a set of corresponding adaptive PCs per each subset is organized. As a result of experiments, the proposed method showed advanced estimation performance compared to both the two 3-band PCA methods and the 5-band wiener method.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.8B
• /
• pp.1424-1435
• /
• 2000

A bit-rate controller that can achieve a constant bit rate when coding object-based video sequences is an important part to achieve an adaptation to bit-rate constraints, desired video quality, distribution of bits among objects, relationship between texture and shape coding, and determination of frame skip or not. Therefore we design content-based bit rate controller which will be used for relevant bit-rate control. The implementation is an extension of MPEG-4 rate control algorithm which employs a quadratic rate-quantizer model. The importance of different objects in a video is analyzed and segmented into a number of VOPs which are adaptively bit-allocated using the object-based modelling. Some test sequences are observed by a number of non-experts and interests in each object are analysed. The initial total target bit-rate for all objects is obtained by using the proposed technique. Then the total target bits are jointly analyzed for preventing from overflow or underflow of the buffer fullness. The target bits are distributed to each object in view of its importance, not only of statistical analysis such as motion vector magnitude, size of object shape, and coding distortion of previous frame. The scheme is compared with the rate controller adopted by the MPEG-4 VM8 video coder by representing their statistics and performance.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.8C
• /
• pp.1113-1124
• /
• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.1
• /
• pp.149-160
• /
• 1997

This paper is concerned with the problem of speaker-adaptive speech synthes is method using a mapped codebook designed by fuzzy mapping on FLVQ (Fuzzy Learning Vector Quantization). The FLVQ is used to design both input and reference speaker's codebook. This algorithm is incorporated fuzzy membership function into the LVQ(learning vector quantization) networks. Unlike the LVQ algorithm, this algorithm minimizes the network output errors which are the differences of clas s membership target and actual membership values, and results to minimize the distances between training patterns and competing neurons. Speaker Adaptation in speech synthesis is performed as follow;input speaker's codebook is mapped a reference speaker's codebook in fuzzy concepts. The Fuzzy VQ mapping replaces a codevector preserving its fuzzy membership function. The codevector correspondence histogram is obtained by accumulating the vector correspondence along the DTW optimal path. We use the Fuzzy VQ mapping to design a mapped codebook. The mapped codebook is defined as a linear combination of reference speaker's vectors using each fuzzy histogram as a weighting function with membership values. In adaptive-speech synthesis stage, input speech is fuzzy vector-quantized by the mapped codcbook, and then FCM arithmetic is used to synthesize speech adapted to input speaker. The speaker adaption experiments are carried out using speech of males in their thirties as input speaker's speech, and a female in her twenties as reference speaker's speech. Speeches used in experiments are sentences /anyoung hasim nika/ and /good morning/. As a results of experiments, we obtained a synthesized speech adapted to input speaker.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1C
• /
• pp.102-110
• /
• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.23 no.6
• /
• pp.706-715
• /
• 2012

Electro-optical sigma-delta modulators are the core module of digital receiver to digitize wideband radio-frequency signals directly at an antenna. Electro-optical sigma-delta modulators use a pulsed laser to oversample an input radio-frequency signals at two Mach-Zehnder Interferometer(MZI) and shape the quantization noise using a fiber-lattice accumulator. Decimation filtering is applied to the quantizer output to construct the input signal with high resolution. The jitter affects greatly on reconstructing the original input signal of modulator. This paper analyzes the performance of first order single bit electro-optical sigma-delta modulator in the time domain and the frequency domain. The performance of modulator is analyzed by using asynchronous spectral averaging of the reconstructed signal's spectrum in the frequency domain. The reference value of time jitter is presented by analyzing the performance of jitter effects. This kind of jitter value can be used as a reference value on the design of modulators.