• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.4
• /
• pp.796-800
• /
• 2011

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.6 no.1
• /
• pp.97-104
• /
• 2011

Pseudo-random sequences with high linear complexity and low correlation function values are widely used in communication and cryptology. In this paper, we study the properties of interleaved sequences generated by shrinking generator. And we give a method for obtaining the shrunken sequence from a partial description of the shrunken sequence by using the phase shifting of PN sequences generated by shrinking generator.

• The KIPS Transactions:PartC
• /
• v.11C no.5
• /
• pp.621-632
• /
• 2004

Recent measurement studies of real teletraffic data in modern telecommunication networks have shown that self-similar (or fractal) processes may provide better models of teletraffic in modern telecommunication networks than Poisson processes. If this is not taken into account, it can lead to inaccurate conclusions about performance of telecommunication networks. Thus, an important requirement for conducting simulation studies of telecommunication networks is the ability to generate long synthetic stochastic self-similar sequences. A new generator of pseu-do-random self-similar sequences, based on the fractional Gaussian nois and a wavelet transform, is proposed and analysed in this paper. Specifically, this generator uses Daubechies wavelets. The motivation behind this selection of wavelets is that Daubechies wavelets lead to more accurate results by better matching the self-similar structure of long range dependent processes, than other types of wavelets. The statistical accuracy and time required to produce sequences of a given (long) length are experimentally studied. This generator shows a high level of accuracy of the output data (in the sense of the Hurst parameter) and is fast. Its theoretical algorithmic complexity is 0(n).

• Journal of applied mathematics & informatics
• /
• v.29 no.1_2
• /
• pp.247-255
• /
• 2011

Invertible functions with a single cycle property have many cryptographic applications. The main context in which we study them in this paper is pseudo random generation and stream ciphers. In some cryptographic applications we need a generator which generates binary sequences of period long enough. A common way to increase the size of the state and extend the period of a generator is to run in parallel and combine the outputs of several generators with different period. In this paper we will characterize a secure quadratic polynomial on $\mathbb{Z}_{2^n}$, which generates a binary sequence of period long enough and without consecutive elements.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.15 no.1
• /
• pp.179-184
• /
• 2020

Cellular automata (CA), which is known as a pseudo random number generator due to its excellent randomness, has various applications. Cho et al. designed a CA-based shrinking generator to generate a long period of nonlinear sequence. In addition, chaotic cat maps have been studied by many researchers as the complex nonlinear dynamics systems with sensitivity in initial conditions and unpredictable characteristics. In this paper, we propose a new image encryption method using nonlinear sequence generated by CA-based shrinking generator with maximum period and 3D chaotic cat map for high security.

• Review of KIISC
• /
• v.2 no.2
• /
• pp.25-30
• /
• 1992

본 논제에서는 원시근과 이차 잉여규를 중심으로 관련되는 암호학에 이용을 언급하기로 한다. 이외에도 이산로그(discrete logarithm), 연분수(conti-nued fraction), 여러 부정방정식(diophantine equation)의 이론등이 암호학에서 빈번히 사용되는 알고리즘의 근간을 이루는 이론들로 알려져 있다. 또한, 유사임의 수열(pseudo-random number sequence)을 만들기 위한 생성자 (generator)들 중에는 정수론에 기초하고 있는 것들이 않이 있다. 제2절에서는 정수의 위수와 원시근에 대한 성질을 논하고, 제 3절에서는 2차 잉여류와 Legender 기호를 소개한 후, 제4절에서 이들이 주로 사용되는 암호학의 분야를 논하기로 한다.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.14 no.5
• /
• pp.1001-1008
• /
• 2019

A high-quality pseudorandom sequence generation is an important part of many cryptographic applications, including encryption protocols. Therefore, a pseudorandom number generator (PRNG) is an essential element for generating key sequences in a cryptosystem. A PRNG must effectively generate a large, high-quality random data stream. It is well known that the bitstreams output by the CA-based PRNG are more random than the bitstreams output by the LFSR-based PRNG. In this paper, we prove that the complemented CA derived from 90/150 maximum length cellular automata(MLCA) is a MLCA to design a PRNG that can generate more secure bitstreams and extend the key space in a secret key cryptosystem. Also we give a method for calculating the cell positions outputting a nonlinear sequence with maximum period in complemented MLCA derived from a 90/150 MLCA and a complement vector.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.17 no.2
• /
• pp.333-342
• /
• 2022

Cellular Automata (CA) is a discrete and abstract computational model that is being applied in various fields. Applicable as an excellent pseudo-random sequence generator, CA has recently developed into a basic element of cryptographic systems. Several studies on CA-based stream ciphers have been conducted and it has been observed that the encryption strength increases when the radius of a CA's neighbor is increased when appropriate CA rules are used. In this paper, among CAs that can be applied as a one-dimensional pseudo-random number sequence generator (PRNG), one-dimensional 5-neighbor CAs are classified according to the connection state of their neighbors, and the ignition relationship of the characteristic polynomial is obtained. Also this paper propose a synthesis algorithm for an asymmetric 1-D linear 5-neighbor MLCA in which the radius of the neighbor is increased by 2 using the one-dimensional 3-neighbor 90/150 CA state transition matrix.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.1
• /
• pp.110-116
• /
• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.11
• /
• pp.84-91
• /
• 2009

A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.