• Computational Structural Engineering
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• v.4 no.1
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• pp.95-108
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• 1991

An explicit finite element method can be executed more rapidly and effectively on vector computer than on the scalar computer because it has suitable structures for vector processing. In this paper, an efficient vectorization method of the explicit finite element program on the memory-to-memory type vector computer is proposed. First, the general vectorization method which can be applied regardless of the vector architecture is investigated, then the method which is suitable for the memory-to-memory type vector computer is proposed. To illustrate the usefulness of the proposed vectorization method, DYNA3D, the existing explicit finite element program, is migrated on HDS AS/XL V50 which is the memory-to-memory type vector computer. Performance results on actual test show a vector/scalar speedup is above 2.4.

• Journal of the Korean Academy of Child and Adolescent Psychiatry
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• v.28 no.2
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• pp.106-114
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• 2017

Objectives: This study was to examine the effectiveness of computerized cognitive ability enhancement program (CCAEP) using Smarttoy. The CCAEP using Smart-toy which can interact with children via bluetooth is a kids-friendly and convenient method for improving children's cognitive abilities by increasing their motivation for performing the program. We developed the CCAEP which designed to train auditory-verbal memory, visual-spatial memory, auditory-verbal working memory, and visual-spatial working memory. Methods: Eighteen children aged 8 to 10 participated in CCAEP individual training composed of 8 sessions of 40 minutes each for 4 weeks. The effect of the training was measured with Smart Toyweb's cognitive assessment tasks (smart device based assessment) as well as traditional neuropsychological tests before and after the training. Results: Children showed significant improvement in auditory-verbal memory, visual-spatial memory, auditory-verbal working memory and visual-spatial working memory abilities after the training. Conclusion: This study demonstrated promising results suggesting the effectiveness of CCAEP using Smart-Toy in clinical settings as well as school and home situations. Further controlled study with larger sample size including various clinical groups is needed to confirm the present results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• Journal of Internet Computing and Services
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• v.14 no.6
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• pp.41-47
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• 2013

GP-GPUs are general purposed GPUs for numerical computation based on multiple threads which are originally for graphic processing. GP-GPUs provide cache memory in a form of shared memory which user programs can access directly, unlikely typical cache memory. In this research, we implemented the parallel block LU decomposition program to utilize cache memory in GP-GPUs. The parallel blocked LU decomposition program designed with Nvidia CUDA C run 7~8 times faster than nun-blocked LU decomposition program in the same GP-GPU computation environment.

• Journal of The Korean Society of Integrative Medicine
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• v.12 no.1
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• pp.83-96
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• 2024

Purpose : This study was conducted to determine the effects of a brain spinning program on cognitive function, body composition, health related fitness and physical self-efficacy of children and adolescents. Methods : This study, 34 children and adolescents were selected and divided into two groups : the exercise group (n=16), which received a brain spinning program and the control group (n=16), which did not receive any exercise program. The program was conducted for 30 minutes three times a week for 4 weeks, and the cognitive function, body composition, health related fitness and physical self-efficacy were measured both before and after the program. Results : The exercise group, which received a brain spinning program showed a significant increase in short-term memory (p<.05) and working memory (p<.01), and muscle mass increased significantly only in the exercise group (p<.05). In addition, left grip strength increased in the exercise group (p<.01), and the maximum oxygen intake decreased significantly only in the control group (p<.05), and Sit-forward bend increased significantly only in the exercise group (p<.01). Physical self-efficacy significantly increased only in the exercise group (p<.05). Conclusion : In summary, short-term memory, cognitive efficiency, working memory, muscle mass, left grip strength, maximum oxygen intake, and left forward bending in children and adolescents significantly increased after the 4-week brain spinning program. However, the control group that was not provided with the 4-week brain spinning program showed a significant increase in body weight and a significant decrease in maximum oxygen intake. In conclusion, the 4-week brain spinning program has positive effects on short-term memory, cognitive function, muscle mass, muscle strength, cardiorespiratory endurance, flexibility, and physical self-efficacy.

• ETRI Journal
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• v.39 no.3
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• pp.428-436
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• 2017

State-of-the-art processors require increasingly complicated memory services for high performance and low power consumption. In particular, they request transfers within a burst in a wrap-around order to minimize the miss penalty of a cache. However, synchronous dynamic random access memories (SDRAMs) do not always generate transfers in the wrap-round order required by the processors. Thus, a memory subsystem rearranges the SDRAM transfers in the wrap-around order, but the rearrangement process may increase memory latency and waste the bandwidth of on-chip interconnects. In this paper, we present a memory subsystem that is effective for the wrapping bursts of a cache. The proposed memory subsystem makes SDRAMs generate transfers in an intermediate order, where the transfers are rearranged in the wrap-around order with minimal penalties. Then, the transfers are delivered with priority, depending on the program locality in space. Experimental results showed that the proposed memory subsystem minimizes the memory performance loss resulting from wrapping bursts and, thus, improves program execution time.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.5
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• pp.55-61
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• 2010

When we design the control system used Programmable Logic Controller(PLC) by Sequential Function Chart(SFC), if we use a SFC, it is easy to know the sequential flow of control, to maintenance the controller and to describe a program. We program a SFC by a unique sequence, an alternative sequence and a parallel sequence. If we program a SFC by a alternative sequence, the memory size of a alternative sequence must be larger than the memory size of a unique sequence. Therefore this thesis show an efficient method to reduce a memory size and we confirmed its feasibility through actual example.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.300-304
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• 2008

A novel characterization method was investigated to estimate the trap generation during the program /erase cycles in nand flash memory cell. Utilizing Fowler-Nordheim tunneling current, floating gate potential and oxide electric field, we established a quantitative model which allows the knowledge of threshold voltage (Vth) as a function of either program or erase operation time. Based on our model, the derived results proved that interface trap density (Nit) term is only included in the program operation equation, while both Nit and oxide trap density (Not) term are included in the erase operation equation. The effectiveness of our model was tested using 50 nm nand flash memory cell with floating gate type. Nit and Not were extracted through the analysis of Program/Erase speed with respect to the endurance cycle. Trap generation and cycle numbers showed the power dependency. Finally, with the measurement of the experiment concerning the variation of cell Vth with respect to program/erase cycles, we obtained the novel quantitative model which shows similar results of relationship between experimental values and extracted ones.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.108-114
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• 2004

In this paper we propose the boot system using CF memory card and study the system implementation method. The system that is proposed in this paper basically consist of high performance microprocessor, small amount of program memory and CF memory card. And added LCD module and touch panel for the user interface. This system use the CF memory card and DRAM instead of the Flash memory, so it can reduce the system cost. And system performance is increased because of the system program running in the DRAM.

• Journal of Information Technology Applications and Management
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• v.31 no.1
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• pp.177-188
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• 2024

In this research, a cohort of two children, aged 7-8 years, was selected to participate in a specialized three-week training program aimed at enhancing their working memory. The program consisted of three sessions, each lasting approximately 30 minutes. The primary goal was to investigate the impact and developmental trajectory of working memory in school-aged children. Working memory plays a significant role in young children's learning and daily activities. To address the needs of this demographic, products should offer both educational and enjoyable activities that engage working memory. Digital educational tools, known for their flexibility, are suitable for both older individuals and young children. By updating software or modifying content, these tools can be effectively repurposed for young learners without extensive hardware changes, making them both cost-effective and practical. For example, memory training games initially designed for older adults can be adapted for young children by altering images, music, or storylines. Furthermore, incorporating elements familiar to children, like animals, toys, or fairy tales, can increase their engagement in these activities. Historically, working memory capabilities have been assessed predominantly through traditional intelligence tests. However, recent research questions the adequacy of these behavioral measures in accurately detecting changes in working memory. To bridge this gap, the current study utilized electroencephalography (EEG) as a more sophisticated and precise tool for monitoring potential changes in working memory after the training. The research findings were revealing. Participants showed marked improvement in their performance on n-back tasks, a standard measure for evaluating working memory. This improvement post-training strongly supports the effectiveness of the training program. The results indicate that such targeted and structured training programs can significantly enhance the working memory abilities of children in this age group, providing promising implications for educational strategies and cognitive development interventions.