• Journal of Broadcast Engineering
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• v.23 no.3
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• pp.431-436
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• 2018

In this paper, a simple but effective algorithm to reduce the computational complexity of thumbnail generation and to improve image quality without aliasing artifacts is proposed. For the high speed decoding, the proposed algorithm performs partial decoding per $4{\times}4$ boundary in TU(Transform Unit), and preforms TU boundary in PU(Prediction Unit). The proposed method defines the weights based on intra prediction directions and estimates the thumbnail pixel by using that weights. this method remains thumbnail extraction time and improves thumbnail image quality compared with conventional algorithms.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.06a
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• pp.149-151
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• 2018

H.265/HEVC(High Efficiency Video Coding)에서는 하드웨어 비디오 인코더의 처리율(Throughput)을 높이기 위하여 동일 CU(Coding Unit) 내 PU(Prediction Unit)들이 병렬로 머지 후보 리스트를 생성할 수 있는 병렬 머지 방법이 표준 기술로 사용되고 있다. 하지만 이 방법은 동일 CU 내의 PU 간의 의존성만 제거할 수 있고 코딩 순서상의 이전 CU 와의 의존성은 제거할 수 없다. 결국 이전 CU 의 모드 결정 과정이 완료된 후에 현재 CU 내의 PU 가 머지 후보 리스트를 생성할 수 있기 때문에 높은 처리율 향상을 기대할 수 없다. 또한 CU 내의 대부분의 PU 들이 가장 인접한 MV(Motion Vector)를 머지 후보로 사용하지 못하여 압축 효율에 대한 손실도 크다. 본 논문에서는 이전 CU 와의 의존성을 제거함으로써 높은 처리율을 갖으면서 압축 효율에 대한 손실을 최소화할 수 있는 개선된 병렬 머지 방법을 제안한다. 실험 결과, 제안된 방법은 기존 병렬 머지 방법 대비 동일 화질에서 평균 약 1.8%의 압축률이 향상되는 것으로 나타났다.

• Journal of Broadcast Engineering
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• v.17 no.5
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• pp.716-724
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• 2012

In this paper, we propose a fast decision method of maximum coding depth decision and reference frame selection in HEVC. To reduce computational complexity and encoding time of HEVC, two methods are proposed. In the first method, the maximum depth of each coding unit (CU) in a largest CU (LCU) is constrained by using the maximum coding depth used by adjacent LCUs based on the assumption that the spatial correlation is very high and rate-distortion (R-D) cost. And we constrain the number of reference pictures for prediction unit (PU) performing motion estimation by using the motion information of the upper depth PU. The proposed methods reduce computational complexity of the HEVC encoder by constraining the maximum coding depth and the reference frame. We could achieve about 39% computational complexity reduction with marginal bitrate increase of 1.2% in the comparison with HM6.1 HEVC reference software.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.293-304
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• 2011

In this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixIII EP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.

• Journal of Korea Multimedia Society
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• v.15 no.4
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• pp.485-491
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• 2012

This paper proposes 'Coding Unit Tree' based on quadtree efficiently with motion vector to represent splitting information of a Coding Unit (CU) in HEVC. The new international video coding, High Efficiency Video Coding (HEVC), adopts various techniques and new unit concept: CU, Prediction Unit (PU), and Transform Unit (TU). The basic coding unit, CU is larger than macroblock of H.264/AVC and it splits to process image-based quadtree with a hierarchical structure. However, in case that there are complex motions in CU, the more signaling bits with motion information need to be transmitted. This structure provides a flexibility and a base for a optimization, but there are overhead about splitting information. This paper analyzes those signals and proposes a new algorithm which removes those redundancy. The proposed algorithm utilizes a type code, a dominant value, and residue values at a node in quadtree to remove the addition bits. Type code represents a structure of an image tree and the two values represent a node value. The results show that the proposed algorithm gains 13.6% bit-rate reduction over the HM-1.0.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.07a
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• pp.462-465
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• 2012

본 논문에서는 HEVC 기술로 부호화된 비디오 비트스트림(HEVC 비트스트림)을 분석하고, 그 결과를 보여주는 방법에 대해서 제안한다.[1] HEVC 기술은 Coding Unit(CU), Prediction Unit(PU), Transform Unit(TU)을 기반으로 부호화가 이루어지므로 부호화 정보를 효과적으로 사용자에게 보여주기 위해서는 CU, PU, TU 를 기반으로 GUI(Graphic User Interface)가 디자인되어야 한다. 제안된 HEVC 비트스트림 분석기에서는 이러한 부호화 구조를 반영하여 사용자 친화적으로 HEVC 비트스트림의 부호화 정보를 편리하게 확인할 수 있도록 하였다.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.354-362
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• 2012

Recently, High Efficiency Video Coding (HEVC) is under development jointly by MPEG and ITU-T for the next international video coding standard. Compared to the previous standards, HEVC supports variety of splitting units, such as coding unit (CU), prediction unit (PU), and transform unit (TU). Among them, it has been known that the recursive quadtree structure of CU can improve the coding efficiency while the encoding complexity is increased significantly. In this paper, a simple conditional probability to predict the early termination condition of recursive unit structure is introduced. The proposed conditional probability is estimated based on Bayes' formula from local statistics of rate-distortion costs in encoder. Experimental results show that the proposed method can reduce the total encoding time by about 32% according to the test configuration while the coding efficiency loss is 0.4%-0.5%. In addition, the encoding time can be reduced by 50% with 0.9% coding efficiency loss when the proposed method was used jointly with HM4.0 early CU termination algorithm.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.11a
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• pp.163-166
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• 2012

본 논문에서는 차세대 비디오 표준인 High Efficiency Video Coding(HEVC)의 영상 부호화 과정의 시간복잡도 감소를 위한 효율적인 Prediction Unit(PU)레벨 움직임예측(Motion Estimation, ME) 병렬화의 구현 기법을 제시하고자 한다. 움직임예측 과정은 부호화기에서 80%의 복잡도를 차지하는 과정으로 고속 부호화의 걸림돌이 되고 있다. 이를 해결하기 위한 방법으로 제안된 것이 움직임예측 알고리즘의 병렬화이다. 알고리즘 수준에서 ME 의 일부인 Merge Estimation 의 병렬화를 위해서 Merge Estimation Region (MER)기반의 ME 방법이 제안되었다. 하지만 HEVC Test Model reference software(HM)에 반영된 MER 을 이용하여 실제로 병렬화된 ME 를 구현하는 과정에서는 알고리즘 측면에서 아직 고려되지 않은 문제들이 존재한다. 이에 본 논문에서는 MER 을 사용한 안정적인 병렬 ME 를 구현하기 위한 전략으로 각 PU 의 정보를 독립적으로 사용하기 위한 부분 순차화 방법과 메모리 접근제한을 이용한 병렬화 방법을 제시한다. 실험을 통해 본 연구의 우수성이 확인되었는데, 제안된 방법에 기반을 둔 구현에서 순차적인 ME 를 이용한 부호화기 대비 평균 25.64%의 전체 부호화 과정 시간의 감소가 나타났다.

• Journal of Broadcast Engineering
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• v.19 no.6
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• pp.836-846
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• 2014

To expedite UHD (Ultra High Definition) video service, the HEVC (High-Efficiency Video Coding) technology has recently been standardized and it achieves two times higher compression efficiency than the conventional H.264/AVC. To obtain the improved efficiency, however, it employs many complex methods which need complicated calculation, thereby resulting in a significantly increased computational complexity when compared to that of H.264/AVC. For example, to improve the coding efficiency of intra frame coding, up to 35 intra prediction modes are defined in HEVC, but this results in an increased encoding time than the H.264/AVC. In this paper, we propose a fast intra prediction mode decision scheme which reduces computational complexity by changing the number of intra prediction mode in accordance with the percentage of PU sizes for a given video resolution, and by classifying the 35 intra prediction modes into 4 categories considering video resolution and quantization parameter. The experimental results show that the total encoding time is reduced by about 7% on average at the cost of only 2% increase in BD-rate.