• Journal of Power Electronics
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• v.7 no.2
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• pp.174-180
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• 2007

In this paper, a simple control method for two-stage utility grid-connected photovoltaic power conditioning systems (PCS) is proposed. This approach enables maximum power point (MPP) tracking control with post-stage inverter current information instead of calculating solar array power, which significantly simplifies the controller and the sensor. Furthermore, there is no feedback loop in the pre-stage converter to control the solar array voltage or current because the MPP tracker drives the converter switch duty cycle. This simple PCS control strategy can reduce the cost and size, and can be utilized with a low cost digital processor. For verification of the proposed control strategy, a 2.5kW two-stage photovoltaic grid-connected PCS hardware which consists of a boost converter cascaded with a single-phase inverter was built and tested.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.360-361
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• 2006

This paper describes a wire and wireless network sensor for temperature and humidity measurements. The network sensor comprises PLC(Power Line Communication) and RF transmitter(433MHz) for acquiring an internal (on-board) sensor signal, and measured data is transmitted to a main processing unit. The network sensor module is consist of MEMS sensor, 10-bit A/D converter, pre-amp., gain-amp., ADUC812 one chip processor and PLC/RF transmitting unit. The temperature and humidity sensor is based on MEMS piezoelectric membrane structure and is implemented by using dual function sensor for smart home and smart building.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.944-949
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• 1986

By improving the ability of arithmatic processing with an arithmatic processor in a microcomputer and realizing the data input system for real time analysis, an FFT analyzer that is usable within the range of audio frequency is designed and constructed. The input signal passes through a gain programmable pre-amplifier and anti-aliasing lowpass filter into an analogditital converter to be converted into digital form. The converted input data is processed by an Apple II microcomputer. The results of the processing are displayed using a microcomputer display unit and can be copied on a printer or stored in a floppy disk.

• Proceedings of the Korea Water Resources Association Conference
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• 2006.05a
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• pp.1444-1449
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• 2006

Korea is about 70% of all country to mountain, and basin is consisted of various terrain, soil, vegetation, land use etc. because use land as intensive. Also, need basin hydrologic model that can analysis base outflow as well as outflow directly for calculation of discharge to establish irrigation plan. Inconvenient in use method and user interface offer side is causing by way that existing USGS WEASEL runs in PC Arc/Info, and ArcGIS with development of present GIS technology is applied in many fields offering convenience in analysis that use GIS. In this research, wished to develop suitable outflow parameter extraction system, For this, develop pre-processor and post-processor that effectively draw of hydrologic model input data from water resources DB through van example benchimarking, and developed input/output component of GIS base applicable to various hydrologic and water quality model.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2888-2897
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• 2011

The performance of a geothermal heat pump system using carbon dioxide was investigated by the steady-state cycle simulation program developed in this study. A parametric study was carried out in order to investigate the effect of various operating conditions on the performance of the basic cycle without an IHX(internal heat exchanger). The simulation program consists of several Fortran subroutines for simulating indoor and outdoor heat exchangers, compressors, and expansion valves and Visual Basic subroutines for the graphic user interface(GUI) consisted with pre-processor for input data and post-processor for the output data. Refprop V6.01 was used for estimating the thermodynamic properties and equilibrium behaviors of carbon dioxide. The simulation results were validated by comparing experimental data through a series of case studies. The cycle simulation program developed in this work would seem to be a useful tool in optimizing and establishing economical and efficient operating conditions in the $CO_2$ geothermal heat pump system.

• Journal of The Korean Society of Agricultural Engineers
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• v.54 no.2
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• pp.115-125
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• 2012

Application of the Object-oriented Programming (OOP) method to the Finite Element Model (FEM) program has various strengths including the features of encapsulation, polymorphism and inheritance. However, this technique should be based upon a premise that the independency of the object method and data to be used is guaranteed. By attempting to apply the OOP to the FEM, existing researches go against the independency of the OOP which is an essential feature of the method. The reason is this: existing researches apply the OOP to modules in accordance with analysis procedures, although the data to be used is classified as an element unit in the FEM. Therefore, the required independency cannot be maintained as whole stiffness matrices and boundary conditions are combined together. Also, solutions are sought from analysis module after data is regrouped at the pre-processor, and their results are analyzed during the post-processor. As this is similar to a batch processing, it cannot use data at analysis, and recalculation should be done from the beginning if any condition is changed after the analysis is complete, which are limitations of the existing researches. This research implemented the Object-orientation of elements so that the three features of the OOP (i.e. encapsulation, polymorphism and inheritance) can be guaranteed and their independency maintained as a result. For this purpose, a model called 'Object-oriented Finite element Model ensuring the Independency of Elements (OFMIE)', which enables the analysis of targets through mutual data exchanges within instance, was developed. In conclusion, the required independency was achieved in the instance of the objected elements and the analysis results of previous conditions could be used for the analysis after changes. The number of repetitive calculations was reduced by 75 per cent through this gradual analysis processes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.778-781
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• 2007

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture protype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.

• Journal of IKEEE
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• v.23 no.4
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• pp.1257-1264
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• 2019

A 3-GSymbol/s/lane transceiver, which supports the mobile industry processor interface (MIPI) C-physical layer (PHY) specification version 1.1, is proposed. It performs channel mismatch correction to improve the signal integrity that is deteriorated by using three-level signals over three channels. The proposed channel mismatch correction is performed by detecting channel mismatches in the receiver and adjusting the delay times of the transmission data in the transmitter according to the detection result. The channel mismatch detection in the receiver is performed by comparing the phases of the received signals with respect to the pre-determined data pattern transmitted from the transmitter. The proposed MIPI C-PHY receiver is designed using a 65 nm complementary metal-oxide-semiconductor (CMOS) process with 1.2 V supply voltage. The area and power consumption of each transceiver lane are 0.136 ㎟ and 17.4 mW/GSymbol/s, respectively. The proposed channel mismatch correction reduces the time jitter of 88.6 ps caused by the channel mismatch to 34.9 ps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.7
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• pp.623-629
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• 2013

This paper presents the implementation result of the EEG(electroencephalogram) signal transmission protocol and its test platform. EEG measured by a dry-type electrode is directly converted into digital signal by ADC(analog-to-digital converter). Thereafter it is transferred DSP(digital signal processor) platform by $I^2C$(inter-integrated circuit) protocol. DSP conducts the pre-processing of EEG and extracts feature vectors of EEG. In this work, we implement the $I^2C$ protocol with 16 channels by using 10 or 12-bit ADC. In the implementation results, the overhead ratio for the 4 bytes data burst transmission measures 2.16 and the total data rates are 345.6 kbps and 414.72 kbps with 10-bit and 12-bit 1 ksps ADC, respectively. Therefore, in order to support a high speed mode of $I^2C$ for 400 kbps, it is required to use 16:1 and $(8:1){\times}2$ ratios for slave:master in 10-bit ADC and 12-bit ADC, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.65-70
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• 2008

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b${\times}$32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.