• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.626-630
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• 1999

A new integrated single-stage zero current switched(ZCS) quasi-resonant converter (QRC) for the power factor correction(PFC) converter is introduced in this paper. The power factor correction can be achieved by the discontinuous conduction mode(DCM) operation of an input current. The proposed converter has the characteristics of the good power factor, low line current harmonics, and tight output regulation. Furthermore, the ringing effect due to the output capacitance of the main switch can be eliminated by use of active clamp circuit.

• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.438-443
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• 1998

A simple single-stage AC/DC forward converter with transformer magnetic energy feedback technique for power factor correction is proposed. The operational principle of the proposed converter is presented. The proposed converter gives the good power factor correction, low line current harmonic distortions, and tight output voltage regulation. The prototype shows high power factor with low line current harmonics.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.179-182
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• 2002

In this paper, 2-stage Power amplifier with external bias controller for\ulcorner IMT-2000 handsets was designed using SiGe HBT with excellent linearity to 1\ulcornereduce size and weight. The designed amplifier has 26.5 dBm output power, 33% power added efficiency, and 22 dB linear power gain in 1920-1980MHz frequency range.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.35-41
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• 2013

An efficient multi-stage rectifier for wireless power transfer in deep implant medical devices is implemented using $0.18-{\mu}m$ CMOS technology. The presented three-stage rectifier employs a cross-coupled topology to boost a small input AC signal from the external device to produce a 1.2-1.5 V output DC signal for the implant device. The designed rectifier achieves a maximum measured power conversion efficiency of 70% at 13.56 MHz under the conditions of a low 0.6-Vpp RF input signal with a $10-k{\Omega}$ output load resistance.

• Proceedings of the KSR Conference
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• 2011.05a
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• pp.1434-1439
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• 2011

The purpose of this study is based on the optimize the system life cycle cost apply to the advanced systems engineering techniques consideration thought to the system life cycle for the power system which is the one of the major component of the light rail transit system. Generally, the systems engineering techniques apply to the LRT's power systems are not optimize the whole life cycle cost of the power systems because systems engineering management activities are concentrate in performing the key-technology oriented at the construction stage of the dedicated power systems for light rail transit. Through this study, All the stakeholders can be utilize a this advanced systems engineering techniques which is fully considered the life cycle cost through the considering in whole system life cycle (such as concept, design, operation, maintenance and dispose stage as well as construction stage) and adopted by KSX ISO/IEC 15288 system life cycle processes.

• Journal of the Korean Society of Industry Convergence
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• v.9 no.4
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• pp.247-253
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• 2006

Power consumption for double-stage paddle impeller in spherical and cylindrical agitated vessel was measured over a wide range of Reynolds number from laminar to turbulent flow regions. The power correlation was obtained which was applied to both spherical and cylindrical vessel, when the apparent diameter of the spherical vessel was equal to the diameter of the cylindrical vessel which had a height equal to its diameter and had the same volume as the spherical vessel. The power consumption for the double-stage impeller was dependent upon the distance of among the impeller in the agitated vessels, as follows: $$f/2={\frac{C_L}{Re_G}}+{\frac{Ct}{2}}({\frac{C_tr}{Re_g}}+Re_g)^{-m}$$

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.308-311
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• 2004

A novel single-stage power factor corrected (PFC) drive for switched reluctance motor (SRM) is presented to achieve sinusoidal, near unity power factor input current. The proposed PFC SRM drive has no additional active switch. And a single-stage approach, which combines a DC link capacitor used as do source and a drive used for driving the motor into one power stage, has a simple structure and low cost. The characteristics and validity of the proposed circuit will be discussed in depth through the experimental results.

• Journal of Power Electronics
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• v.15 no.1
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• pp.78-85
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• 2015

This paper presents a new structure of single-stage flyback power factor correction (PFC) converter with a controllable coupled negative magnetic feedback (NMF) winding. NMF winding is used to reduce the bulk capacitor voltage at high line voltages and light loads. However, it would cause line current distortion at zero crossing condition. In the proposed circuit, a series winding is used with NMF inductor to eliminate the NMF inductor at low line voltages. As a result, the dead angle of the input current, near zero voltage crossing, is eliminated and the power factor is increased. The presented experimental results of the proposed PFC converter confirm the integrity of the new idea and the theoretical analysis.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.235-238
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• 2001

A novel single-stage power factor corrected (PFC) drive for switched reluctance motor (SRM) is presented to achieve sinusoidal, near unity power factor input current. The proposed PFC SRM drive has no additional active switch. And a single-stage approach, which combines a DC link capacitor used as dc source and a drive used for driving the motor into one power stage, has a simple structure and low cost. The characteristics and validity of the proposed circuit will be discussed in depth through the experimental results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.235-245
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• 2014

This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.