• 한국전기전자재료학회논문지
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• 제29권5호
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• pp.263-267
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• 2016

In this paper, we analyzed the electrical characteristics of NPT planar and trench gate IGBT after designing these devices according to design and process parameter. To begin with, we have designed NPT planar gate IGBT and carried out simulation with T-CAD. Therefore, we extracted design and process parameter and obtained optimal electrical characteristics. The breakdown voltage was 724 V and The on state voltage drop was 1.746 V. The next was carried out optimal design of trench gate power IGBT. We did this research by same drift thickness and resistivity of planar gate power IGBT. As a result of experiment, we obtain 720 V breakdown voltage, 1.32 V on state voltage drop and 4.077 V threshold voltage. These results were improved performance and fabrication of trench gate power IGBT and planar gate Power IGBT.

• 한국전기전자재료학회논문지
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• 제25권4호
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• pp.270-275
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• 2012

Power MOSFET(metal oxide silicon field effect transistor) operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. But on-resistance characteristics depending on the increasing breakdown voltage spikes is a problem. So 600 V planar power MOSFET compare to 1/3 low on-resistance characteristics of super junction MOSFET structure. In this paper design to 600 V planar MOSFET and super junction MOSFET, then improvement of comparative analysis breakdown voltage and resistance characteristics. As a result, super junction MOSFET improve on about 40% on-state voltage drop performance than planar MOSFET.

• 한국전기전자재료학회논문지
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• 제23권9호
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• pp.671-675
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• 2010

Gallium nitride (GaN), wide bandgap semiconductor, has attracted much attention because they are projected to have much better performance than silicon. In this paper, effects of design parameters change of GaN power static induction transistor (SIT) on the electrical characteristics (breakdown voltage, on resistance) were analyzed by computer simulation. According to the analyzed results, the optimization was performed to get power GaN SIT that has 600 V class breakdown voltage. As a result, we could get optimized 600 V class power GaN SIT that has higher breakdown voltage and lower On resistance with a thin (a several micro-meters) thickness of the channel layer.

• 한국전기전자재료학회논문지
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• 제30권3호
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• pp.148-151
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• 2017

This research concerns field rings for 3.3kV planar gate power insulated-gate bipolar transistors (IGBTs). We design an optimal field ring for a 3.3kV power IGBT and analyze its electrical characteristics according to field ring parameters. Based on this background, we obtained 3.3kV high breakdown voltage and a 2.9V on state voltage drop. To obtain high breakdown voltage, we confirmed that the field ring count was 23, and we obtained optimal parameters. The gap distance between field rings $13{\mu}m$ and the field ring width was $5{\mu}m$. This design technology will be adapted to field stop IGBTs and super junction IGBTs. The thyristor device for a power conversion switch will be replaced with a super high voltage power IGBT.

• 한국전기전자재료학회논문지
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• 제29권2호
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• pp.75-78
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• 2016

This research was designed 700 level power MOSFET for smart LED driver ICs package. And we analyzed electrical characteristics of the power MOSFET as like breakdown voltage, on-resistance and threshold voltage. Because this research is important optimal design for smart LED ICs package, we designed power MOSFET with design and process parameter. As a result of this research, we obtained $60{\mu}m$ N-drift layer depth, 791.29 V breakdown voltage, $0.248{\Omega}{\cdot}cm^2$ on resistance and 3.495 V threshold voltage. We will use effectively this device for smart LED driver ICs package.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1146-1148
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• 1995

To improve the breakdown characteristics of vertical power devices, field limiting ring(FLR) is popularly used. In this paper, at vertical power device having $300{\sim}600V$ breakdown voltage, FLR thecnique is considered, by two dimensional computer simulator, with the various of parameters; number of FLR, seperation distance of first FLR from the main juncton and second FLR from the first FLR, doping concentration and thickness of epi-layer, etc.. Below $40{\mu}m$ epi thickness, and for the case of one FLR, the maximum breakdown voltage, 580V is obtained.

• 전기학회논문지
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• 제56권7호
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• pp.1282-1287
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• 2007

We investigated the damage of the CMOS IC which manufactured three different technologies by high power microwave. The tests separated the two methods in accordance with the types of the CMOS IC located inner waveguide. The only CMOS IC which was located inner waveguide was occurred breakdown below the max electric field (23.94kV/m) without destruction but the CMOS IC which was connected IC to line organically was located inner waveguide and it was occurred breakdown and destruction below the max electric field. Also destructed CMOS IC was removed their surface and a chip condition was analyzed by SEM. The SEM analysis of the damaged devices showed onchuipwire and bondwire destruction like melting due to thermal effect. The tested results are applied to the fundamental data which interprets the combination mechanism of the semiconductors from artificial electromagnetic wave environment and are applied to the data which understand electromagnetic wave effects of electronic equipments.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.439-442
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• 2002

The interface between two different materials in the insulation systems is the weak-link in the underground power transmission systems, In this paper, Optimum conditions of the interface between Epoxy and EPDM is studied. The variation factor condition of interface is roughness of surface, spreading of oils, interfacial pressure and temperature. The breakdown times under the constant voltage below the breakdown voltage were also gained. The breakdown voltage at the after laying time equivalent to is calculated by the V-t characteristic and the inverse power law. When this is done, the characteristic life exponent n is used and the long time breakdown voltage can be evaluated.

• 전기전자학회논문지
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• 제22권3호
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• pp.565-569
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• 2018

For the conventional power MOSFET (metal-oxide semiconductor field-effect transistor) device structure, there exists a tradeoff relationship between specific on-state resistance (Ron,sp) and breakdown voltage (BV). In order to overcome this tradeoff, a super-junction (SJ) trench MOSFET (TMOSFET) structure with uniform or non-uniform doping concentration, which decreases linearly in the vertical direction from the N drift region at the bottom to the channel at the top, for an optimal design is suggested in this paper. The on-state resistance of $0.96m{\Omega}-cm2$ at the SJ TMOSFET is much less than that at the conventional power MOSFET under the same breakdown voltage of 100V. A design methodology for the edge termination is proposed to achieve the same breakdown voltage and on-state resistance as the main body of the super-junction TMOSFET by using of the SILVACO TCAD 2D device simulator, Atlas.

• 대한전자공학회논문지
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• 제27권7호
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• pp.1033-1041
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• 1990

In this paper, under pinch-off conditions, the gate-drain breakdown voltage characteristics of GaAs Power MESFET's as a function of device parameters such as channel thickness, doping concentration, gate length etc. are analyzed. Using the Green's function, the gate ionic charge induced by the depleted channel ionic charge is calculated. The impact ionization integral by avalanche multiplication between gate and drain is used to investigate breakdown phenomena. Especially, the localized excess surface charge effect as well as the uniform surface charge effect on breakdown voltage is considered.