• The Pure and Applied Mathematics
• /
• v.25 no.4
• /
• pp.253-265
• /
• 2018

In this paper, we introduce the concept of Fibonacci sequences on MV-algebras and study them accurately. Also, by introducing the concepts of periodic sequences and power-associative MV-algebras, other properties are also obtained. The relation between MV-algebras and Fibonacci sequences is investigated.

• Communications of the Korean Mathematical Society
• /
• v.37 no.3
• /
• pp.649-658
• /
• 2022

In this paper, we introduce the notion of a left-almost-zero groupoid, and we generalize two axioms which play important roles in the theory of BCK-algebra using the notion of a projection. Moreover, we investigate a Smarandache disjointness of semi-leftoids.

• The KIPS Transactions:PartA
• /
• v.12A no.3 s.93
• /
• pp.205-214
• /
• 2005

Flash memory is at high speed used as storage of personal information utilities, ubiquitous computing environments, mobile phones, electronic goods, etc. This is because flash memory has the characteristics of low electronic power, non-volatile storage, high performance, physical stability, portability, and so on. However, differently from hard disks, it has a weak point that overwrites on already written block of flash memory is impossible to be done. In order to make an overwrite possible, an erase operation on the written block should be performed before the overwrite, which lowers the performance of flash memory highly. In order to solve this problem the flash memory controller maintains a system software module called the flash translation layer(FTL). Of many proposed FTL schemes, the log block buffer scheme is best known so far. This scheme uses a small number of log blocks of flash memory as a write buffer, which reduces the number of erase operations by overwrites, leading to good performance. However, this scheme shows a weakness of low page usability of log blocks. In this paper, we propose an enhanced log block buffer scheme, FAST(Full Associative Sector Translation), which improves the page usability of each log block by fully associating sectors to be written by overwrites to the entire log blocks. We also show that our FAST scheme outperforms the log block buffer scheme.

• The KSFM Journal of Fluid Machinery
• /
• v.5 no.4 s.17
• /
• pp.47-53
• /
• 2002

The steam generator feedwater flow-rate in a nuclear power plant was estimated by means of artificial neural networks with the wavelet analysis for enhanced information extraction. The fouling of venturi meters, used for steam generator feedwater flow-rate in pressurized water reactors, may result in unnecessary plant power derating. The back-propagation network was used to generate models of signals for a pressurized water reactor Multiple-input, single-output hetero-associative networks were used for evaluating the feedwater flow rate as a function of a set of related variables. The wavelet was used as a low pass filter eliminating the noise from the raw signals. The results have shown that possible fouling of venturi can be detected by neural networks, and the feedwater flow-rate can be predicted as an alternative to existing methods. The research has also indicated that the decomposition of signals by wavelet transform is a powerful approach to signal analysis for denoising.

• Journal of the Korea Fashion and Costume Design Association
• /
• v.20 no.1
• /
• pp.49-59
• /
• 2018

The purpose of this research is to study the semantic characteristics of men's cosmetics brand names by analyzing 51 brand names in the domestic market, so as to find ways to develop strategic brand names. In order to investigate this area, the study looked at the Interbrand Company's Name Spectrum, and the results are as follows. The men's cosmetics brand names turned out to be freestanding brand names, descriptive brand names, and associative brand names, in that order. The freestanding brand names were found to be the initial combinations of the words that have the desired benefits in the concepts of the pertinent brands; in other words, coined brand names that were made by synthesizing words such as nice men, naturalism, eco-friendly plant-derived materials and ideal skin. Associative brand names are generally used to express the effect of enhancing brand awareness by considering the phonetic image of the word or prompting a masculine and favorable image. Descriptive brand names use language symbols such as men, homme, man, monsieur and gentle to represent specific business and product categories for men, and also use stem, plant, flower, skin, beauty, moisturizing, tosowoong and so on to provide the properties and beneficial information related to the products. In conclusion, the men's cosmetics brand names embody an important factor that symbolizes the concepts, functions or features of the brand, and there is a need for men's cosmetic brands to develop more unique and distinctive brand names to promote their brand names as constitutional factors that can build brand power and strengthen brand image.

• Journal of KIISE:Computing Practices and Letters
• /
• v.15 no.1
• /
• pp.1-13
• /
• 2009

Flash memory is widely used as a storage medium of mobile devices such as MP3 players, cellular phones and digital cameras due to its tiny size, low power consumption and shock resistant characteristics. Currently, there are many studies to replace HDD with flash memory because of its numerous strong points. To use flash memory as a storage medium, FTL(Flash Translation Layer) is required since flash memory has erase-before-write constraints and sizes of read/write unit and erase unit are different from each other. Recently, new type of flash memory called "large block flash memory" is introduced. The large block flash memory has different physical structure and characteristics from previous flash memory. So existing FTLs are not efficiently operated on large block flash memory. In this paper, we propose an efficient FTL for large block flash memory based on FAST(Fully Associative Sector Translation) scheme and page-level mapping on data blocks.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.2
• /
• pp.75-84
• /
• 2005

This research is to design a high performance NAND-type flash memory package with a smart buffer cache that enhances the exploitation of spatial and temporal locality. The proposed buffer structure in a NAND flash memory package, called as a smart buffer cache, consists of three parts, i.e., a fully-associative victim buffer with a small block size, a fully-associative spatial buffer with a large block size, and a dynamic fetching unit. This new NAND-type flash memory package can achieve dramatically high performance and low power consumption comparing with any conventional NAND-type flash memory. Our results show that the NAND flash memory package with a smart buffer cache can reduce the miss ratio by around 70% and the average memory access time by around 67%, over the conventional NAND flash memory configuration. Also, the average miss ratio and average memory access time of the package module with smart buffer for a given buffer space (e.g., 3KB) can achieve better performance than package modules with a conventional direct-mapped buffer with eight times(e.g., 32KB) as much space and a fully-associative configuration with twice as much space(e.g., 8KB)

• Journal of the Korea Society of Computer and Information
• /
• v.16 no.10
• /
• pp.1-10
• /
• 2011

There are the large overhead of block erase and page write operations in NAND flash memory, though it has low power consumption, cheap prices and a large storage. Due to the physical characteristics of NAND flash memory, overwrite operations are not permitted at the same location, so rewriting operation require after erase operation. it cause performance decrease of NAND flash memory. Using SRAM buffer in traditional NAND flash memory, it can not only reduce effective write operation but also guarantee fast memory access time. In this paper, we proposed the small SRAM buffer management system for reducing overhead of NAND flash memory, that is, erase and write operations. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer with the small fetching block size and a fully associative spatial buffer with the large fetching block size. The temporal buffer have small fetching blocks that referenced from spatial buffer. When it happen write operations or erase operations in NAND flash memory, the related fetching blocks in temporal buffer include a page or a block are written in NAND flash memory at the same time. The writing and erasing counts in NAND flash memory can be reduced. According to the simulation results, although we have high miss ratios, write and erase operations can be reduced approximatively 58% and 83% respectively. Also the average memory access times are improved about 84% compared with the fully associative buffer with two sizes.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.11
• /
• pp.56-62
• /
• 2008

Modern microprocessors must deliver high application performance, while the design process should not subordinate power. In terms of performance and power tradeoff, the instructions window is particularly important. This is because a large instruction window leads to achieve high performance. However, naive scaling conventional instruction window can severely affect the complexity and power consumption. This paper explores an architecture level approach to reduce power dissipation. We propose a low power issue logic with an efficient tag translation. The direct lookup table (DTL) issue logic eliminates the associative wake-up of conventional instruction window. The tag translation scheme deals with data dependencies and resource conflicts by using bit-vector based structure. Experimental results show that, for SPEC2000 benchmarks, the proposed design reduces power consumption by 24.45% on average over conventional approach.

• Journal of the Korea Society of Computer and Information
• /
• v.18 no.12
• /
• pp.1-9
• /
• 2013

Even though the multiple pages TLB are effective in improving the performance, a conventional method with OS support cannot utilize multiple page sizes in user application. Thus, we propose a new multiple-TLB structure supporting multiple page sizes for high performance and low power consumption without any operating system support. The proposed TLB is organised as two parts of a S-TLB(Small TLB) with a small page size and a L-TLB(Large TLB) with a large page size. Both are designed as fully associative bank structures. The S-TLB stores small pages are evicted from the L-TLB, and the L-TLB stores large pages including a small page generated by the CPU. Each one bank module of S-TLB and L-TLB can be selectively accessed base on particular one and two bits of the virtual address generated from CPU, respectively. Energy savings are achieved by reducing the number of entries accessed at a time. Also, this paper proposed the simple 1-bit LRU policy to improve the performance. The proposed LRU policy can present recently referenced block by using an additional one bit of each entry on TLBs. This method can simply select a least recently used page from the L-TLB. According to the simulation results, the proposed TLB can reduce Energy * Delay by about 76%, 57%, and 6% compared with a fully associative TLB, a ARM TLB, and a Dual TLB, respectively.