• Journal of Korea Society of Digital Industry and Information Management
• /
• v.11 no.3
• /
• pp.45-51
• /
• 2015

In this paper, we discuss the belief propagation decoding algorithm for polar codes. The performance of Polar codes for shorter lengths is not satisfactory. Motivated by this, we propose a novel technique to improve its performance at short lengths. We showed that the probability of messages passed along the factor graph of polar codes, can be increased by multiplying the current message of nodes with their previous message. This is like a feedback path in which the present signal is updated by multiplying with its previous signal. Thus the experimental results show that performance of belief propagation polar decoder can be improved using this proposed technique. Simulation results in binary-input additive white Gaussian noise channel (BI-AWGNC) show that the proposed belief propagation polar decoder can provide significant gain of 2 dB over the original belief propagation polar decoder with code rate 0.5 and code length 128 at the bit error rate (BER) of $10^{-4}$.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.3
• /
• pp.427-435
• /
• 2015

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

• ETRI Journal
• /
• v.46 no.3
• /
• pp.485-500
• /
• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.5
• /
• pp.550-556
• /
• 2016

Polar codes are one of the most favorable capacity-achieving codes due to their simple structure and low decoding complexity. However, because of the disappointing decoding performance realized using conventional successive cancellation (SC) decoders, polar codes cannot be used directly in practical applications. In contrast to conventional SC decoders, list SC (SCL) decoders with large list sizes (e.g. 32) achieve performances very close to those of maximum-likelihood (ML) decoders. In SCL decoders with large list sizes, however, hardware increase is a severe problem because an SCL decoder with list size L consists of L copies of an SC decoder. In this paper, we present a low-area SCL decoder architecture that applies the proposed merged processing element-sharing (MPES) algorithm. A merged processing element (MPE) is the basic processing unit in SC decoders, and the required number of MPEs is L(N-1) in conventional SCL decoders. Using the proposed algorithm reduces the number of MPEs by about 70% compared with conventional SCL decoders when the list size is larger than 32.

• Journal of IKEEE
• /
• v.24 no.2
• /
• pp.550-558
• /
• 2020

Successive cancellation (SC) decoding that is one of the decoding algorithms for polar codes has long decoding latency and low throughput because of the nature of successive decoding. To reduce the latency and increase the throughput, various decoding structures for polar codes are presented. In this paper, we compare the previous decoding structures and analyze them by dividing into two types, pruning and multi-path decoders. Decoders for applying pruning are representative of SSC (simplified SC), Fast-SSC and redundant-LLR structures, and decoders with multi-path are representative of 2-bit SC and redundant-LLR structures. All the previous structures are compared in terms decoding latency and hardware area, and according to the comparison, the syndrome check based decoder has the lowest latency and redundant-LLR decoder has the highest hardware efficiency.

• Journal of electromagnetic engineering and science
• /
• v.11 no.4
• /
• pp.239-249
• /
• 2011

In this paper, we propose a reliable $8{\times}8$ up-down switching polar relay code based on 3GPP LTE standard, motivated by 3GPP LTE down link, which is 30 bps/Hz for $8{\times}8$ MIMO antennas, and by Arikan's channel polarization for the frequency selective fading (FSF) channels with the generator matrix $Q_8$. In this scheme, a polar encoder and OFDM modulator are implemented sequentially at both the source node and relay nodes, the time reversion and complex conjugation operations are separately implemented at each relay node, and the successive interference cancellation (SIC) decoder, together with the cyclic prefix (CP) removal, is performed at the destination node. Use of the scheme shows that decoding at the relay without any delay is not required, which results in a lower complexity. The numerical result shows that the system coded by polar codes has better performance than currently used designs.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38C no.1
• /
• pp.109-117
• /
• 2013

Polar codes are the first provable error correcting code achieving the symmetric channel capacity in a wide case of binary input discrete memoryless channel(BI-DMC). However, finite length polar codes have an error floor problem with successive-cancellation list(SCL) decoder. From previous works, we can solve this problem by concatenating CRC(Cyclic Redundancy Check) codes. In this paper we propose to make polar codes having extended-minimum distance from original polar codes without outer codes using correlation with generate matrix of polar codes and that of RM(Reed-Muller) codes. And we compare performance of proposed polar codes with that of polar codes concatenating CRC codes.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.16 no.2
• /
• pp.658-675
• /
• 2022

This paper presents a fast-simplified successive cancellation (SC) flipping (Fast-SSC-Flip) decoding algorithm for polar code. Firstly, by researching the probability distribution of the number of error bits in a node caused by channel noise in simplified-SC (SSC) decoder, a measurement criterion of node reliability is proposed. Under the guidance of the criterion, the most unreliable nodes are firstly located, then the unreliable bits are selected for flipping, so as to realize Fast-SSC-Flip decoding algorithm based on node reliability (NR-Fast-SSC-Flip). Secondly, we extended the proposed NR-Fast-SSC-Flip to multiple node (NR-Fast-SSC-Flip-ω) by considering dynamic update to measure node reliability, where ω is the order of flip-nodes set. The extended algorithm can correct the error bits in multiple nodes, and get good performance at medium and high signal-to-noise (SNR) region. Simulation results show that the proposed NR-Fast-SSC-Flip decoder can obtain 0.27dB and 0.17dB gains, respectively, compared with the traditional Fast-SSC-Flip [14] and the newly proposed two-bit-flipping Fast-SSC (Fast-SSC-2Flip-E2) [18] under the same conditions. Compared with the newly proposed partitioned Fast-SSC-Flip (PA-Fast-SSC-Flip) (s=4) [18], the proposed NR-Fast-SSC-Flip-ω (ω=2) decoder can obtain about 0.21dB gain, and the FER performance exceeds the cyclic-redundancy-check (CRC) aided SC-list (CRC-SCL) decoder (L=4).

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.18 no.5
• /
• pp.1412-1430
• /
• 2024

The soft cancellation list (SCANL) decoding algorithm for polar codes runs L soft cancellation (SCAN) decoders with different decoding factor graphs. Although it can achieve better decoding performance than SCAN algorithm, it has high latency. In this paper, a fast simplified SCANL (Fast-SSCANL) algorithm that runs L independent Fast-SSCAN decoders is proposed. In Fast-SSCANL decoder, special nodes in each factor graph is identified, and corresponding low-latency decoding approaches for each special node is propose first. Then, syndrome check aided Fast-SSCANL (SC-Fast-SSCANL) algorithm is further put forward. The ordinary nodes satisfied the syndrome check will execute hard decision directly without traversing the factor graph, thereby reducing the decoding latency further. Simulation results show that Fast-SSCANL and SC-Fast-SSCANL algorithms can achieve the same BER performance as the SCANL algorithm with lower latency. Fast-SSCANL algorithm can reduce latency by more than 83% compared with SCANL, and SC-Fast-SSCANL algorithm can reduce more than 85% latency compared with SCANL regardless of code length and code rate.