• Title/Summary/Keyword: pipelining

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High-Speed FPGA Implementation of SATA HDD Encryption Device based on Pipelined Architecture (고속 연산이 가능한 파이프라인 구조의 SATA HDD 암호화용 FPGA 설계 및 구현)

  • Koo, Bon-Seok;Lim, Jeong-Seok;Kim, Choon-Soo;Yoon, E-Joong;Lee, Sang-Jin
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.22 no.2
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    • pp.201-211
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    • 2012
  • This paper addresses a Full Disk Encryption hardware processor for SATA HDD in a single FPGA design, and shows its experimental result using an FPGA board. The proposed processor mainly consists of two blocks: the first block processes XTS-AES block cipher which is the IEEE P1619 standard of storage media encryption and the second block executes the interface between SATA Host (PC) and Device (HDD). To minimize the performance degradation, we designed the XTS-AES block with the 4-stage pipelined structure which can process a 128-bit block per 4 clock cycles and has 4.8Gbps (max) performance. Also, we implemented the proposed design with Xilinx ML507 FPGA board and our experiment showed 140MB/sec read/write speed in Windows XP 32-bit and a SATA II HDD. This performance is almost equivalent with the speed of the direct SATA connection without FDE devices, hence our proposed processor is very suitable for SATA HDD Full Disk Encryption environments.