• 제목/요약/키워드: phase error

검색결과 2,006건 처리시간 0.032초

고전압 전기용량 브지리와 표준용량분압기를 이용한 전자식 전압변성기의 평가 (Evaluation of Errors of Electronic Voltage Transformer using High Voltage Capacitance Bridge and Standard Capacitive divider)

  • 한상길;김윤형;정재갑;강전홍;이상화;한상옥
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2008년도 추계학술대회 논문집 전기설비전문위원
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    • pp.61-63
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    • 2008
  • We established a system to evaluate the ratio error and phase angle error of electronic voltage transformer using high voltage capacitance bridge and standard capacitors. The uncertainty of evaluation system is about 0.005% in ratio error and 1.5 min in phase angel error.

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A New In-band Full-duplex SIC Scheme Using a Phase Rotator

  • Lee, Haesoon;Kim, Dongkyu;Kim, Jinmin;Hong, Daesik
    • IEIE Transactions on Smart Processing and Computing
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    • 제3권4호
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    • pp.240-245
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    • 2014
  • How well the self-interference cancellation (SIC) technique performs is a primary issue in realizing an in-band full-duplex (FD) wireless communication system. One factor affecting its performance is channel estimation error on the self-interference channel. We propose a new analog SIC scheme which is robust to channel estimation error. It uses phase rotators in the radio frequency (RF) chain. We also derive closed-form equations for the residual self-interference of the proposed and the conventional schemes. The analytical and numerical results show that the residual self-interference under the proposed SIC scheme is less than that using the conventional scheme, even though channel estimation error is present.

멀티패스 채널 환경하에서 NEC 구조를 이용한 ${\pi}/4$ shift QPSK ([ ${\pi}/4$ ] shift QPSK for NEC structure in multipath channels)

  • 편용국;강기성;임황빈;심상홍;윤상옥
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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    • pp.1212-1216
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    • 2003
  • In this study, the ${\pi}/4$ shift QPSK(quadrature phase shift keying) with NEC(nonredundant error correction) on the multipath channel can detect the burst error as well as random error one by using the second and L-th order phase difference. Therefore, the BER(bit error rate) performance in ${\pi}/4$ shift QPSK is more improved than that of the ${\pi}/4$ shift QPSK without NEC structure. Also, this performance become a bit better in Rayleigh fading channel.

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Voltage Source Inverter Drive Using Error-compensated Pulse Width Modulation

  • Chen, Keng-Yuan;Hu, Jwu-Sheng;Lin, Jau-Nan
    • Journal of Power Electronics
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    • 제16권1호
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    • pp.388-397
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    • 2016
  • An error-compensated pulse width modulator (ECPWM) is proposed to improve the baseband harmonic performance and the switching loss of voltage source inverters (VSIs). Selecting between harmonic distortion and switching loss is a design tradeoff in the conventional space vector pulse width modulation. In this work, an accumulated difference in produced and desired phase voltages is considered to adjust the reference signal. This mechanism can compensate for the voltage error in the previous carrier period. With error compensation every half-carrier period, the proposed ECPWM allows one-half reduction in carrier frequency without scarifying baseband harmonic distortion. The proposed modulator is applied to a three-phase VSI with R-L load and a motor-speed-control system for experiments. The measured efficiency and operating temperature of switches confirm the effectiveness of the proposed scheme.

위상도플러 유속계를 이용한 계측에 있어서의 화염에 기인한 오차의 평가 (The evaluation of error due to flame in the measurement using phase doppler anemometry)

  • 양영준
    • 센서학회지
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    • 제14권5호
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    • pp.313-321
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    • 2005
  • Spray combustion has been used in many industrial fields, for instance, such as diesel engines, gas turbines and industrial furnaces, and furthermore various measurement techniques have been applied to elucidate the phenomenon of spray combustion. In order to measure simultaneously the droplet velocity and the droplet size of spray, phase doppler anemometry (PDA) was frequently used in spray combustion. However, the measurement error is occurred due to existence of flame, which is considered as influencing the precision of measurement. Therefore, the purpose of this study is experimentally to conduct the systematic evaluation on the measurement error when PDA measurement is applied to combustion field.

광디스크 드라이브를 위한 강인 제어기 설계 (Robust Servo System for Optical Disk Drive Systems)

  • 박범호;정정주;표현봉;박용우
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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    • pp.380-383
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    • 2003
  • This paper proposes a new and simple input prediction method for robust servo system. This servo system uses robust tracking control system based on both Coprime Factorization(CF) and Zero Phase Error Tracking control system. The CF control system can be designed simply and systematically. Moreover, this system has not only stability but also robustness and disturbance rejection ability The optical disk tracking servo system can detect only the tracking error. So the new and simple input prediction system proposed in this paper estimates the reference input signal from the tracking error. Numerical simulation results show that the proposed method is effective.

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수중음향통신에서 효율적인 패킷 설계에 관한 연구 (A Study on Efficient Packet Design for Underwater Acoustic Communication)

  • 박태두;정지원
    • 한국항해항만학회지
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    • 제36권8호
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    • pp.631-635
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    • 2012
  • 수중에서의 통신은 해수면과 해저면 등에 의한 신호의 반사가 생겨 다중경로 전달현상이 발생한다. 이러한 다중경로 전달의 영향으로 신호는 왜곡되고 원활한 수신을 방해하게 된다. 본 논문에서는 이러한 다중경로 환경에서 효율적인 패킷 설계를 위하여 채널 부호화 기법으로는 부호화 후의 크기 N = 1944 비트, 전송하고자 하는 데이터의 크기 K = 972 비트를 가지는 부호화율 1/2 인 LDPC(Low Density Parity Check codes) 부호를 이용하였으며, 다중경로로 인한 위상 오차 추정은 decision directed 방식을 이용하여 위상 추정을 하였다. 실제 동해 바다에서 송수신 거리가 200m, 500m 그리고 데이터 속도를 1Kbps, 4Kbps로 설정하여 각 거리 및 데이터 속도에 따른 QEF(Quasi Error Free)가 되는 지점에서의 최적의 패킷 구성을 위한 데이터 길이를 제시하였다.

Design of Gain Controller of Decoupling Control of Grid-connected Inverter with LCL Filter

  • Windarko, Novie Ayub;Lee, Jin-Mok;Choi, Jae-Ho
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2008년도 추계학술대회 논문집
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    • pp.124-126
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    • 2008
  • Grid Connected inverter is produced current to deliver power to grid. To provide low THD current, LCL filters is effective to filter high frequency component of current output from inverter. To provide sinusoidal waveform, there are many researchers have been proposed several controllers for grid-connected inverter controllers. Synchronous Reference Frame (SRF)-based controller is the most popular methods. SRF-based controller is capable for reducing both of zero-steady state error and phase delay. But SRF based controller is contained cross-coupling components, which generate some difficulties to analyze. In this paper, SRF based controller is analyzed. By applying decoupling control, cross-coupling component is eliminated and single phase model of the system is obtained. Through this single phase model, gain controller is designed. To reduce steady state error, proportional gain is set as high as possible, but it may produce instability. To compromise between a minimum steady state error and stability, the single phase model is evaluate through Root Locus and Bode diagram. PSIM simulation is used to verify the analysis.

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5-GHz Delay-Locked Loop Using Relative Comparison Quadrature Phase Detector

  • Wang, Sung-Ho;Kim, Jung-Tae;Hur, Chang-Wu
    • Journal of information and communication convergence engineering
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    • 제2권2호
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    • pp.102-105
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    • 2004
  • A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 um Standard CMOS process and it operates at 5 GHz frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

2단 양자화기를 사용한 1차 DPLL의 성능 개선에 관한 연구 (A Study on the Performance of a Modified Binary Quantized first-Order DPLL)

  • 강치우;김진헌
    • 대한전자공학회논문지
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    • 제21권3호
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    • pp.6-12
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    • 1984
  • 기존의 2단 양자화된 1차 디지탈 위상포착회로(DPLL)의 포착시간과 정상상태에서의 위상오차를 줄이기 위한 방법을 연구하였다. 기본적인 DPLL에 하향(falling) 영전위교차시간을 검출하여 위상을 교정하는 회로를 첨가하여 그 성능을 개선하기 위한 연구를 하였으며 기본적인 DPLL의 성능과 비교하였다. 그래프방식을 사용하여 잡음이 없는 상태에서 위상스텝 및 주파수 스텝입력에 대한 DPLL의 위상포착과정을 시각적으로 해석하였다. 정현파 입력에 협대역임의잡음(narrow band random noise)이 섞여 있을 때 DPLL의 성능을 분석하기 위해서 Chapman-Kolmogorov 방정식을 사용하였다. 이 방법은 컴퓨터에 의한 모의 시험을 통하여 입증되었다. 수정된 DPLL의 정상상태의 위상오차와 평균포착시간이 기본적인 DPLL의 그것들과 비교되었다. 수정된 DPLL의 포착시간은 거의 두 배 정도 빨라졌으며 정상상태의 위상오차는 신호대잡음비가 커짐에 따라 개선의 폭이 중가하여 결국 영에 접근함을 알 수 있었다.

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