• Title/Summary/Keyword: path algebra

Search Result 22, Processing Time 0.016 seconds

A Study On The Adaptive Equalizer Of Coefficient Adjustment In Mobile Communication Systems (이동 통신 시스템에서 조정 계수를 이용한 적응 등화기에 관한 연구)

  • 전상규;김노환
    • Journal of the Korea Society of Computer and Information
    • /
    • v.1 no.1
    • /
    • pp.53-64
    • /
    • 1996
  • The methods for designing the adaptive filter performing DSP(digital signal processing)functions In mobile communication systems are Least-squares algorithm. Fast-Kalman and adaptive lattice algorithm. Least-squares algorithm It fast convergence algorithm for signal Processor of adaptive equallizer and used for eliminating inter symbol Interference which occur inmultiple path fading channel In mobille communication systems. In this paper. we propose the method of control adjustably algebra characteristics of signal vector that is sampling at some of new data sequence and confirm the improvement of fast convergence and iterative performance speed compared to existing algorithms by computer simulation.

  • PDF

Incremental Techniques for Timing Analysis Considering Timing and Circuit Structure Changes (지연시간과 회로 구조 변화를 고려한 증가적 타이밍 분석)

  • O, Jang-Uk;Han, Chang-Ho
    • The Transactions of the Korea Information Processing Society
    • /
    • v.6 no.8
    • /
    • pp.2204-2212
    • /
    • 1999
  • In this paper, we present techniques which perform incremental timing analysis using Timed Boolean Algebra that solves the false path problem and extracts the timing information in combinational circuits. Our algorithm sets histories of internal inputs that are substituted for internal output and extracts maximal delays through checking sensitizability of primary outputs. Once finding the sum of primitive delay terms, then it applies modified delay with referencing histories of primary output and it can extract maximal delays of primary outputs fast and efficiently. When the structure of circuit is changed, there is no need to compute the whole circuit again. We can process partial timing analysis of computing on the gates that are need to compute again. These incremental timing analysis methods are considered both delay changes and structure of circuit, and can reduce the costs of a trial error in the circuit design.

  • PDF