• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.2
• /
• pp.302-317
• /
• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.3
• /
• pp.205-210
• /
• 2001

In this paper, a novel compound mode logic based on the advantage of both CMOS logic and pass-transistor logic(PTL) is proposed. From the experimental results, the power-delay products of the compound mode logic is about 22% lower than that of the conventional CMOS logic, when we design a full adder. With the proposed logic, a high performance 32$\times$32-bit multiplier has been fabricated with 0.6um CMOS technology. It is composed of an improved sign select Booth encoder, an efficient data compressor based on the compound mode logic, and a 64-bit conditional sum adder with separated carry generation block. The Proposed 32$\times$32-bit multiplier is composed of 28,732 transistors with an active area of 1.59$\times$1.68 mm2 except for the testing circuits. From the measured results, the multiplication time of the 32$\times$32-bit multiplier is 9.8㎱ at a 3.3V power supply, and it consumes about 186㎽ at 100MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.6
• /
• pp.447-458
• /
• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.3
• /
• pp.51-51
• /
• 2001

본 논문에서는 CMOS 로직과 pass-transistor logic(PTL)의 장점만을 가진 새로운 복합모드로직(Compound Mode Logic)을 제안하였다. 제안된 로직은 VLSI설계에서 중요하게 부각되고 있는 저전력, 고속 동작이 가능하며 실제로 전가산기를 설계하여 측정 한 결과 복합모드 로직의 power-delay 곱은 일반적인 CMOS로직에 비해 약 22% 개선되었다 제안한 복합모드 로직을 이용하여 고성능 32×32-bit 곱셈기를 설계 제작하였다. 본 논문의 곱셈기는 개선된 사인선택(Sign Select) Booth 인코더, 4-2 및 9-2 압축기로 구성된 데이터 압축 블록, 그리고 carry 생성 블록을 분리한 64-bit 조건 합 가산기로 구성되어 있다. 0.6um 1-poly 3-metal CMOS 공정을 이용하여 제작된 32×32-bit 곱셈기는 28,732개의 트랜지스터와 1.59×l.68 ㎜2의 면적을 가졌다. 측정 결과 32×32-bit 곱셈기의 곱셈시간은 9.8㎱ 이었으며, 3.3V 전원 전압에서 186㎽의 전력 소모를 하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.4
• /
• pp.60-70
• /
• 2000

An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.