• 전기전자학회논문지
• /
• 제1권1호
• /
• pp.11-18
• /
• 1997

회로 시뮬레이터를 이용하는 DC 셀 노드전압 분석방법을 적용하여, 고저항 SRAM 셀 구조에서 기생저항들과 트랜지스터 비대칭에 의해 야기되는 정적 읽기동작에서의 동작마진을 조사하였다. 이상적인 셀에 기생저항을 선택적으로 추가함으로써 각 기생저항들이 동작 마진에 끼치는 영향을 조사한 뒤, 기생저항이 좌우대칭 쌍으로 존재하는 경우에 대해 조사하고, 또한 셀 트랜지스터의 채널폭을 선택적으로 변화시켜 트랜지스터의 비대칭을 야기시킴으로써 트랜지스터 비대칭에 의한 동작 마진의 저하를 분석하였다. 분석 방법은 시뮬레이션된 셀 노드전압 특성에서 두 셀 노드전압이 하나의 값으로 수렴되는 전원전압의 값과 $V_{DD}=5V$에서 셀 노드전압의 차를 비교함으로써 상대적인 동작 마진을 비교하는 방법을 사용하였다. 회로 시뮬레이션에 의존한 본 분석으로부터 셀의 정적 읽기동작에 가장 심각한 영향을 끼치는 기생저항 성분과 트랜지스터의 비대칭 형태를 규명함으로써 새로운 셀 구조 설계시 참고할 수 있는 기준을 제시하였다.

• Parasites, Hosts and Diseases
• /
• 제60권5호
• /
• pp.309-315
• /
• 2022

Inflammatory bowel disease (IBD) is a chronic and recurrent illness of the gastrointestinal tract. Treatment of IBD traditionally involves the use of aminosalicylic acid and steroids, while these drugs has been associated with untoward effects and refractoriness. The absence of effective treatment regimen against IBD has led to the exploration of new targets. Parasites are promising as an alternative therapy for IBD. Recent studies have highlighted the use of parasite-derived substances, such as excretory secretory products, extracellular vesicles (EVs), and exosomes, for the treatment of IBD. In this report, we examined whether EVs secreted by Giardia lamblia could prevent colitis in a mouse model. G. lamblia EVs (GlEVs) were prepared from in vitro cultures of Giardia trophozoites. Clinical signs, microscopic colon tissue inflammation, and cytokine expression levels were detected to assess the effect of GlEV treatment on dextran sulfate sodium (DSS)-induced experimental murine colitis. The administration of GlEVs prior to DSS challenge reduced the expression levels of pro-inflammatory cytokines, including tumor necrosis factor alpha, interleukin 1 beta, and interferon gamma. Our results indicate that GlEV can exert preventive effects and possess therapeutic properties against DSS-induced colitis.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2001년도 하계학술대회 논문집 C
• /
• pp.1896-1898
• /
• 2001

An offset problem caused by the static parasitic capacitors is analyzed and then some techniques to reduce their effect on the capacitive position sensor are presented. Also new offset compensation technique is proposed that by adjusting the magnitudes of the modulating signals independently, the charge imbalance between electrodes caused by the parasitic capacitors is eliminated without sensor gain variation. Simulation results are given to validate the proposed compensation technique.

• 한국산업정보학회:학술대회논문집
• /
• 한국산업정보학회 2002년도 춘계학술대회 논문집
• /
• pp.195-199
• /
• 2002

This paper describes the effect of substrate back bias of CMOS Inverter. When the substrate back bias applied in body, the MOS transistor threshold voltage increased and drain saturation current decreased. The back gate reverse bias or substrate bias has been widely utilized and the following advantage has suppressing subthreshold leakage, lowering parasitic junction capacitance, preventing latch up or parasitic bipolar transistor, etc. When the reverse voltage applied substrate, this paper stimulated the propagation delay time CMOS inverter.

• 미생물학회지
• /
• 제8권4호
• /
• pp.173-177
• /
• 1970

In this study the effect of aerosol for the control of the parasitic Aspergilli in the sericultural room was investigated. The results obtained are summarized as follows : 1) The aerosol of PPS-A and PPS-B were quite effective for the control of parasitic Aspergilli in the room of sericulture, while the solution of formalin and chlor kalk, on the other hand, were inconclusive. 2) The activities of the aerosol of PPS-A and PPS-B are more effective when it is applied on the upper part of the room than the lower.

• 전기학회논문지
• /
• 제65권5호
• /
• pp.785-793
• /
• 2016

This paper analyzes an LCL-type isolated dc-dc converter operating for constant output voltage in the continuous conduction mode(CCM) with resistances of parasitic losses-static drain-source on resistance of power switch, ESR of resonant network(L-C-L)-using a high loaded quality factor Q assumptions and fourier series techniques. Simple analytical expressions for performance characteristics are derived under steady-state conditions for designing and understanding the behavior of the proposed converter. The voltage-driven rectifier is analyzed, taking into account the diode threshold voltage and the diode forward resistance. Experimental results measured for a proposed converter at low input voltage and various load resistances show agreement to the theoretical performance predicted by the analysis within maximum 4% error. Especially in the case of low output voltages and large loads, It is been observed that introduction of both rectifier and the parasitic components of converter had considerable effect on the performance.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1998년도 추계학술대회 논문집
• /
• pp.13-16
• /
• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• 전자공학회논문지A
• /
• 제33A권2호
• /
• pp.148-162
• /
• 1996

Bonding wires for high frequency device packaging have dominant parasitic inductances which limit the performance of semiconductor lasers. In this paper, the inductance sof bonding wires are claculated by the method of moments with incorporation of ohmic loss, and the wideband modulation characteristics are analyzed for ddifferent wire lengths and structures. We observed the modulation bandwidth for 1mm-length bonding wire lengths and structures. We observed the modulation bandwidth for 1mm-length bonding wire is 7 GHz wider than that for 2mm-length bonding wire. We also observed th estatic inductance calculation results in dispersive deviation of the parasitic inductance and the modulation characteristics from the wideband moment methods calculations. The angled bonding wire has much less parasitic inductance and improves the modulation bandwidth more than 6 GHz. This calculation resutls an be widely used for designing and packaging of high-speed semiconductor device.

• Transactions on Electrical and Electronic Materials
• /
• 제4권2호
• /
• pp.15-19
• /
• 2003

In this paper, the new dual trench gate Emitter Switched Thyristor (DTG-EST) is proposed for improving snap-back effect which leads to a lot of serious problems of device applications. Also the parasitic thyristor that is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and 35A/$\textrm{cm}^2$, respectively. But the proposed DTG-EST exhibits snap-back with the anode voltage and current density 0.96V and 100A/$\textrm{cm}^2$, respectively.

• 전기학회논문지
• /
• 제67권4호
• /
• pp.538-542
• /
• 2018

In order to generate a clock source with low cost and high performance in system on chip(SoC), a relaxation oscillator with stable output characteristics according to PVT(process, voltage and temperature) fluctuation require a low area and a low power. In this paper, we propose a solution to reduce the current loss caused by parasitic components in the conventional relaxation oscillator. Since the slew rate of the bias current and the capacitor are adjusted to be the same through the proposed solution, a relaxation oscillator with low area characteristics is designed for the same clock source frequency implementation. The proposed circuit is designed using the TSMC CMOS 0.18um process. The Simulation results show that the relaxation oscillator using the proposed solution can prevent the current loss of about $279{\mu}A$ and reduce the total chip area by 20.8% compared with the conventional oscillator in the clock source frequency of 96 MHz.