• 전자공학회논문지A
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• 제31A권4호
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• pp.30-38
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• 1994

In this paper, we propose the parallel scrambling technique which is applicable in the multibit-interleaved multiplexing environment. For this, we introduce the concept of SSRG (simple shift register generator) and MSRG(modular shift register generator), and investigate their properties. We also introduce the concept of PSRG(parallel shift register generator) - parallel form of shift register generator, and consider realizations of PSRGs based on SSRGs and MSRGs. Finally, we show how to apply PSRGs to the parallel scrambling for the SDH system.

• 정보처리학회논문지A
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• 제8A권3호
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• pp.253-260
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• 2001

공유 변수를 가지는 병렬 프로그램의 오류 수정에서 경합 탐지는 중요하다. 왜냐하면, 경합은 프로그램의 비결정적인 수행을 유발하기 때문이다. 기존에 제시된 병렬 프로그램의 오류 수정 기법인 수행중 탐지 기법은 내포된 병렬 프로그램에서 최초 경합 탐지를 보장할 수 없다. 최초 경합을 수정하면 이후에 발생하는 경합들이 나타나지 않을 수 있으므로, 최초경합의 탐지는 중요하다. 본 논문에서는 내포 병렬 루프 프로그램을 대상으로 반복 수행을 통해서 최초경합을 탐지하는 기법을 제시한다. 반복 수행의 횟수는 최악의 경우에 프로그램의 내포 깊이 만큼이며 각 수행시의 효율성은 공유변수의 개수를 V, 프로그램의 최대 병렬성을 T라 할 때, 공간 복잡도 O(VT)와 시간 복잡도 O(T)를 가지므로 기존의 수행중 탐지 기법과 동일하다. 그러므로 본 기법은 효과적이고 실용적인 오류 수정을 가능하게 한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.196-198
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• 2007

A circuit design technique to reduce the propagation time is proposed for the analog parallel processing-based Viterbi decoder. The analog Viterbi decoder implements the function of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The decoder is for the PR(1.2,2.1) signal of DVD. The benefits are low power consumption and less silicon occupation. In this paper, a propagation time reduction technique is proposed by minimizing the parasitic capacitance components in the layout design of the analog Viterbi decoder. The propagation time reduction effect of the proposed technique has been shown via HSPICE simulation.

• 전자공학회논문지B
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• 제33B권5호
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• pp.41-51
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• 1996

In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.

• 대한임베디드공학회논문지
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• 제11권1호
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• pp.21-27
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• 2016

An integrated display software platform for small UAV is developed based on parallel processing technique in this paper. When the small UAV with high-performance camera and avionic modules is employed to various surveillance-related missions, it is important to reduce the operator's workload and increase the monitoring efficiency. For this purpose, it is needed to develop an efficient monitoring software enable to manipulate the image and flight data obtained during flight within the given processing time and display them simultaneously. In this paper, we set up requirements and suggest the architecture for the software platform. The integrated software platform is implemented with parallel processing scheme. Based on AR drone, we verified that the various data are concurrently displayed by the suggest software platform.

• 한국환경과학회지
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• 제15권3호
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• pp.261-269
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• 2006

In this study, an optimization technique was developed from the application of allocation rule. The results obtained from the water supply analysis and reliability indices analysis of Andong dam and Imha dam which are consist of parallel reservoir system are summarized as the followings; Allocation rule(C) is effective technique at the parallel reservoir system because results of the water supply analysis, storage analysis and reliability indices analysis is calculated reasonable results. Also, reliability indices analysis results are not sufficient occurrence based reliability or quantity based reliability. Thus reliability indices analysis are need as occurrence based reliability, quantity based reliability vulnerability, resilience, average water supply deficits and average storage. And water supply condition is better varying water supply condition than constant water supply condition.

• 조명전기설비학회논문지
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• 제14권6호
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• pp.12-17
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• 2000

IN induction heating system the high frequency operation allows a rapid response to current fluctuation in the inverter and result in improved welding quality. To work induction heating of nonferrous metals, a welding power supply is need high working frequency and high power. This paper is shown design technique for increasing working frequency in induction heating for welding coppers. A series-parallel resonate inverter consists of H-type bridges, each of whose arms is composed of a combination of two parallel IGBTs. Inverter operating with the fixed frequency is controlled by pulse width modulation (PWM). As switching adapted the Zero-Voltage Switching technique to reduce switching losses the system is high efficiency. The propose inverter has feature which is high efficiency for very wide load variations with a narrow range of duty cycle ratio control and load short circuit capability. Detailed experimental results obtained from a 48[V] output, 500[W] experimental inverter are presented to verify the concept.

• 한국공작기계학회논문집
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• 제13권3호
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• pp.44-52
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• 2004

This paper proposed a error compensation methodology for three-DOF translational parallel manipulator. The proposed method uses CMM (coordinate measuring machine) as metrology equipment to measure the position of end-effector. To identify the transform relationships between the coordinate system of the parallel manipulator and the CMM coordinate system, a new coordinate referencing (or coordinate system identification) technique is presented. By using this technique, accurate coordinate transformation relationships are efficiently established. According to these coordinate transformation relationships, an equation to calculate the compensating error components at any arbitrary position of the end-effector is derived. In this paper, Monte Carlo simulation method is applied to simulate the compensation process. Through the simulation results, the proposed error compensation method proves its effectiveness and feasibility.

• 한국통신학회논문지
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• 제21권2호
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• pp.383-393
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• 1996

This paper considers the evaluation of the ecquistion performance for an accesschannel preamble based on a random access procedure of direct sequence code division multiple access(DS/CDMA) reverse link. The parallel acquistion technique that employs the single-well detection scheme and the multiple-dwell(double-dwell) detection scheme is mentioned. The acquisition performance for two detection schemes is compared in therms of the acquisition probability and the acquisition time. The parallel acquisition is done by a bank of N parallel I/Q noncoherent correlators. Expressions on the detection, false alarm, and miss probabilities of the single-dwell and multiple-dwell(double-well) detection schemes are derived for multiple H$_{1}$ cells and multipath Rayleight fading channel. comparing the single-dwell detection scheme with the multiple-dwell(double-dwell) detection scheme in the case of employing the parallel acquisition technique in the reverse link,the numerical results show that the single-dwell detection scheme deomonstrates a better performance.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제11권6호
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• pp.167-174
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• 2022

PIPO 경량 블록암호는 ICISC'20에서 발표된 암호이다. 본 논문에서는 32-bit RISC-V 프로세서 상에서 PIPO 경량 블록암호 ECB, CBC, CTR 운용 모드의 단일 블록 최적화 구현과 병렬 최적화 구현을 진행한다. 단일 블록 구현에서는 32-bit 레지스터 상에서 효율적인 8-bit 단위의 Rlayer 함수 구현을 제안한다. 병렬 구현에서는 병렬 구현을 위한 레지스터 내부 정렬을 진행하며, 서로 다른 4개의 블록이 하나의 레지스터 상에서 Rlayer 함수 연산을 진행하기 위한 방법에 대해 설명한다. 또한 CBC 운용모드의 병렬 구현에서는 암호화 과정에 병렬 구현 기법 적용이 어렵기 때문에 복호화 과정에서의 병렬 구현 기법 적용을 제안하며, CTR 운용모드의 병렬 구현에서는 확장된 초기화 벡터를 사용하여 레지스터 내부 정렬 생략 기법을 제안한다. 본 논문에서는 병렬 구현 기법이 여러 블록암호 운용모드에 적용 가능함을 보여준다. 결과적으로 ECB 운용모드에서 키 스케줄 과정을 포함하고 있는 기존 연구 구현의 성능 대비 단일 블록 구현에서는 1.7배, 병렬 구현에서는 1.89배의 성능 향상을 확인하였다.