• Journal of the Korean Operations Research and Management Science Society
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• v.39 no.4
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• pp.19-31
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• 2014

We study parallel processing techniques for the R programming language of high performance computing technology. In this study, we used massively parallel computing system which has 25,408 cpu cores. We conducted a performance evaluation of a distributed memory system using MPI and of a the shared memory system using OpenMP. Our findings are summarized as follows. First, For some particular algorithms, parallel processing is about 150 times faster than serial processing in R. Second, the distributed memory system gets faster as the number of nodes increases while shared memory system is limited in the improvement of performance, due to the limit of the number of cpus in a single system.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.87-89
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• 2005

This paper proposes new series and parallel Sin+Cos PSS(power system stabilizer) for the purpose to improve the existing PSS1A's performance. The purpose of PSS is used to enhance damping of power system oscillations through injection of auxiliary signal for an excitation control terminal. The Proposed series and Parallel Sin+Cos PSS is connected adding the Sin+Cos terms additionally with serial and with parallel connection in a conventional PSS1A. The proposed controller is aim to considering of a damping of oscillation when it changes parameter fluctuations or operational load variations in a power system. The object of electric power system is KEPCO system and the voltage of power transmission line is a 154kV and a 345kV. The PSCAD/EMTDC package is used to authorize the effect of the proposed controller. Simulations were shown by and compared with the waveforms for frequency, voltage and electric power.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.3
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• pp.235-241
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• 2020

In this paper, we propose the bus/bypass synchronization phase lock loop (B-Sync PLL) method using each phase voltage controller of a parallel UPS inverter. The B-Sync PLL included in each phase voltage control system of parallel UPS inverters has the transient response and the phase synchronization error at grid normal or blackout. The validity of this method is verified by simulation and experiment. As a result, the parallel UPS inverters using the proposed method confirmed that the output phase was continuously synchronized when a grid blackout, improving the transient response characteristics for stable load power supply and equal load sharing.

• Journal of Power System Engineering
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• v.17 no.3
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• pp.50-56
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• 2013

The analysis of performance characteristics was carried out in the plate type evaporator with counter and parallel flow. To investigate performance of evaporator with water inlet temperature and refrigerant mass flow rate were changed. As a result, when the inlet temperature of water is $8^{\circ}C$, capacity of parallel flow evaporator higher than counter flow is 0.35%. But as the inlet temperature of water rises from $8^{\circ}C$ to $16^{\circ}C$, capacity of counter flow type evaporator higher than parallel flow type is 0.12%, 0.27%, 1.1%, 1.6%, respectively. The findings showed that counter flow type evaporator has a larger capacity than those that were parallel flow type evaporator. As the refrigerant mass flow rate rises, capacity and pressure drop increases in the counter and parallel flow type evaporator.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.2
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• pp.55-59
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• 2002

Parallel processing is able to be used effectively on computationally intense power system problems. But this technology is not still available is not only parallel computer but also parallel processing scheme. Testing these algorithms to ensure accuracy, and evaluation of their performance is also an issue. Although a significant amount of parallel algorithms of power system problem have been developed in last decade, actual testing on parallel computer architectures lies in the beginning stages because no clear cut paths. This paper presents Jacobian modeling method to supply the base being able to treat power flow by newton's method by the computer. This method is to assign and to compute teared blocks of sparse matrix at each parallel processors. The testing to insure accuracy of developed method have been done on serial computer by trying to simulate a parallel environment.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.5
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• pp.41-51
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• 1996

In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.402-405
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• 2004

In this paper, the parallel operation of the IGBT and power stack for easy capacity enlargement series in the medium power capacity inverter system of the 660V voltage class is described. The parallel operation of the IGBT and power stack for 1.5MVA medium power inverter system's design is applied. The results of the parallel operation are described in this paper. The designed stack capacity for parallel operation is 800kVA class. For 1.5MVA inverter system, the 800kVA stack is applied with 2 parallel configurations. The 800kVA stack is designed with 3 parallel configurations of the IGBT Module. In this paper, the feasibility for easy capacity enlargement series in the medium power inverter by applying the parallel operation of the IGBT and power stack is verified. The experimental results show the good characteristics for the parallel operation of the IGBT and power stack.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.1051-1052
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• 2010

• 한국전산유체공학회:학술대회논문집
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• 2001.05a
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• pp.149-154
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• 2001

Parallel performance of a Myrinet based PC-cluster was tested and compared with a conventional Fast-Ethernet system. A preconditioned Navier-Stokes code was parallelized with domain decomposition technique, and used for the parallel performance test. Speed-up ratio was examined as a major performance parameter depending on the number of processor and the network topology. As was expected, Myrinet system shows a superior parallel performance to the Fast-Ethernet system even with a single network adpater for a dual processor SMP machine. A test for the dependency on problem size also shows that network communication speed is a crucial factor for parallelized computational fluid dynamics analysis and the Myrinet system is a plausible candidate for high performance parallel computing system.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.1
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• pp.122-129
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• 2005

On the cluster system, the parallel code of rigid-plastic FEM has been developed. The cluster system, Simforge, has 15 processors and the total memory is 4.5GBytes. In the developed parallel code, the distributed data of the column-wise partitioned stiffness are stored as the compressed row storage and the diagonal preconditioned conjugate gradient solver is applied. The analysis of block upsetting is performed with the parallel code on Simforge cluster system. In this paper, the analysis results are compared and discussed.