• International Journal of Contents
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• 제1권1호
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• pp.50-58
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• 2005

Generally, multidimensional data such as image and spatial data require large amount of storage space. There is a limit to store and manage those large amounts of data in single workstation. If we manage the data on parallel computing environment which is being actively researched these days, we can get highly improved performance. In this paper, we propose a parallel multidimensional index structure that exploits the parallelism of the parallel computing environment. The proposed index structure is nP(processor)-nxmD(disk) architecture which is the hybrid type of nP-nD and 1P-nD. Its node structure in-creases fan-out and reduces the height of an index. Also, a range search algorithm that maximizes I/O parallelism is devised, and it is applied to k-nearest neighbor queries. Through various experiments, it is shown that the proposed method outperforms other parallel index structures.

• Journal of information and communication convergence engineering
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• 제11권4호
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• pp.298-306
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• 2013

The scale invariant feature transform (SIFT) is an effective algorithm used in object recognition, panorama stitching, and image matching. However, due to its complexity, real-time processing is difficult to achieve with current software approaches. The increasing availability of parallel computers makes parallelizing these tasks an attractive approach. This paper proposes a novel parallel approach for SIFT algorithm implementation using a block filtering technique in a Gaussian convolution process on the SIMD Pixel Processor. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and input/output capabilities of the processor, which results in a system that can perform real-time image and video compression. We apply this implementation to images and measure the effectiveness of such an approach. Experimental simulation results indicate that the proposed method is capable of real-time applications, and the result of our parallel approach is outstanding in terms of the processing performance.

• 한국전자파학회논문지
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• 제25권3호
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• pp.357-364
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• 2014

본 연구에서는 빠르게 전자파 해석을 수행할 수 있는 병렬 유한차분 시간영역(Finite-Difference Time-Domain: FDTD) 알고리즘을 구현하기 위하여 CPU 클러스터를 구축하였다. 병렬 FDTD 알고리즘은 단일 프로세서를 이용한 FDTD 알고리즘에 비해 해석 시간을 크게 줄일 수 있으며, 전기적으로 매우 큰 구조물에 대한 전자파 해석도 가능하다. 본 연구팀에서는 CPU 클러스터 기반의 병렬 FDTD 알고리즘에서 요구되는 프로세스 간의 통신을 위해 MPI(Message Passing Interface) 라이브러리를 이용하였으며, 3차원 공간분할을 적용하여 프로세스 간의 통신 시간을 최소화하였다. 단일 프로세서를 이용한 FDTD 알고리즘 대비 CPU 클러스터 기반의 병렬 FDTD 알고리즘의 계산속도 향상도를 기본 모드와 하이퍼 모드에서 분석하였으며, 전기적으로 매우 큰 콘크리트 구조물의 전자파 해석을 하였다.

• 한국전자통신학회논문지
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• 제13권2호
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• pp.333-340
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• 2018

본 논문은 병렬 CRC 생성 방식을 적용한 BCH 코드 복호기를 소개한다. 기존에 사용되는 병렬 신드롬 생성기로 LFSR(: Linear Feedback Shift Register)을 변형한 방식을 사용하면 짧은 길이의 코드에 적용하는 데 많은 면적을 차지한다. 제안하는 복호기는 짧은 길이 코드워드의 복호화를 위해 병렬 CRC(: Cyclic Redundancy Check)에서 체크섬을 계산하는 데 사용되는 방식을 활용하였다. 이 방식은 병렬 LFSR과 비교해 중복된 xor연산을 제거해 최적화된 조합회로로 크기가 작고 짧은 전파지연을 갖는다. 시뮬레이션 결과 기존 방식 대비 최대 2.01ns의 지연시간 단축 효과를 볼 수 있다. 제안하는 복호기는 $0.35-{\mu}m$ CMOS 공정을 이용하여 설계하고 합성되었다.

• International Journal of Contents
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• 제1권1호
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• pp.40-44
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• 2005

This paper introduces region partitioning method of non-perfect nested loops with non-uniform dependences. This kind of loop normally can't be parallelized by existing parallelizing compilers and transformations. Even when parallelized in rare instances, the performance is very poor. Based on the Convex Hull theory which has adequate information to handle non-uniform dependences, this paper proposes an enhanced region partitioning method which divides the iteration space into minimum parallel regions where all the iterations inside each parallel region can be executed in parallel by using variable renaming after copying.

• 한국지능정보시스템학회:학술대회논문집
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• 한국지능정보시스템학회 2006년도 춘계학술대회
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• pp.303-310
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• 2006

The sorting algorithms have been developed to take advantage of distributed computers. But the speedup of parallel sorting algorithms decrease rapidly with increased number of processors due to parallel processing overhead such as context switching time and inter-processor communication cost. In this paper, we propose a parallel sorting method which provides linear speedup of an optimal serial algorithm for a system with a large number of processors. This algorithm may even provide superlinear speedup for a practical system. The algorithm takes advantage of an interconnection network properties and its protocol.

• 한국경영과학회:학술대회논문집
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• 대한산업공학회/한국경영과학회 1991년도 춘계공동학술대회 발표논문 및 초록집; 전북대학교, 전주; 26-27 Apr. 1991
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• pp.6-22
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• 1991

This thesis presents a parallel implementation of an iterative method for large scale, sparse linear system and gives result of computational experiments performed on both single transputer and multi transputer parallel computers. To solve linear system, we use conjugate gradient method and develope data storage techinique, data communication scheme. In addition to the explanation of conjugate gradient method, the result of computational experiment is summarized.

• 한국산업정보학회논문지
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• 제3권1호
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• pp.258-268
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• 1998

This paper presents two sequential advanced split and merge algorithms and a parallel image segmentation algorithm based on them. First, the two advanced methods are obtained from the combination of edge detection and classic split and merge to solve the inherent problems of the classical method. Besides, the parallel image segmentation algorithm on mesh-connected MIMD system considers three types in the merge stage to reduce the communication overhead between processors, such as intraprocessor merge, interprocessor with boundary merge, and interprocessor without boundary merge. Finally , we prove that the proposed algorithms achieve the improved performance by implementing them.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 A
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• pp.233-236
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• 2001

Parallel operation scheme to several transformers is adopted because of the load increase, economic problem, or load shedding. For the transformer's parallel operation, loads proportional to each transformer's capacity must be allotted, and circulation currents must be limited as much as without causing any problem in a real operation. But, both transformers in parallel operation can be tripped when either faults at lower voltage side of a transformer or faults in a bus occurs. Therefore, parallel operation scheme to distribution transformers in Korea is not adopted in a normal state but only when loaded or load-shedded. These are due to the insufficiency of the construction in communication network and AVR scheme. Besides that, those are because bus bar protection scheme to lower voltage side of a transformer is not applied. In spite of enormous initial investment costs, advanced countries take so much account of power system reliability and stable supply that they adopt the parallel operation scheme in a normal state. One of the problems in parallel operation is the overheat of transformers due to the excessive circulation currents. This paper presents the scheme that controls voltages between both transformers using circulation currents that occurs in parallel operation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.277-278
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• 2005

Admittance Spectroscopic analysis was applied to study the effect of LiF buffer layer and to model the equivalent circuit for poly(2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylenevinylene) (MEH-PPV)-based polymer light emitting diodes (PLEDs) with the LiF cathode buffer layer. The single layer device with ITO/MEH-PPV/Al structure can be modeled as a simple parallel combination of resistor and capacitor. Insertion of a LiF layer at the Al/MEH-PPV interface shifts the highest occupied molecular orbital level and the vacuum level of the MEH-PPV layer as a result the barrier height for electron injection at the Al/MEH-PPV interface is reduced. The admittance spectroscopy measurement of the devices with the LiF cathode buffer layer shows reduction in contact resistance ($R_c$), parallel resistance ($R_p$) and increment in parallel capacitance ($C_p$).