• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.393-396
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• 2001

In this paper, a new type of linearizer using a parallel diode with a bias feed resistance has been studied. It has positive gain and negative phase deviations because of a nonlinearity of the diode and movement of bias point cause by a voltage drop at the bias feed resistance. This predistortion linearizer consists of the little component and miniaturizes circuit design. The characteristics of this linearizer can be easily tuned using input bias voltage. In fabricated linearizer, maximum gain and Phase deviation of the linearizer is 1dB, 21$^{\circ}$ respectively. By applying its characteristics to the power amplifier, it will be linearized power amplifier.

• Journal of Internet Computing and Services
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• v.4 no.5
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• pp.51-60
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• 2003

Asynchronous iteration is a way to reduce performance degradation of some parallel algorithms due to load imbalance or transmission delay between computing nodes, which requires asymmetric communication between the nodes of different speeds. To implement such asynchronous communication on distributed memory systems, we suggest an MPMD method that creates an additional separate server process on each computing node, and compare it with an SPMD method that creates a single process per node.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.33-34
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• 2016

This paper presents a load sharing method based on the low bandwidth communication (LBC) applied to a DC microgrid in order to balance the state of charge (SOC) of the battery units connected in parallel to the common bus. In this method, SOC of each battery unit is transferred to each other through LBC to calculate average SOC value. After that, droop coefficients of battery units are adjusted according to the difference between SOC of each unit and average SOC value of all batteries in the system. The proposed method can effectively balance the SOC of battery units in charging and discharging duration with a simple low bandwidth communication system.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.6
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• pp.31-37
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• 2008

In order to organize the Intelligent Transport System(ITS) as a communication equipment, the satellite and wireless system demand broadband characteristics for collecting information from the wide road. Band-pass filters (BPF) or broad BPFs used in such communication system are required for broadband characteristics. This paper presents a design of such broad BPF which can be used in the system. Designed BPF which was difficult to get broadband characteristics after realization, become possible to realize filter with broad bandwidth and compact structure using parallel coupled line. The designed filter achieved the insertion losses improved by 0.4 dB and the return losses improved by 17.4 dB respectively with 60% of bandwidth at the 5.8 GHz of the center frequency, respectively.

• ETRI Journal
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• v.39 no.4
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• pp.570-581
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• 2017

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.19-22
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• 2005

As the optical communication industry is developed, the demand of optical communication part is increasing. $ZrO_2$ ceramic ferrule is very important part which can determines the transmission efficiency and information quality to connect the optical fibers. In general $ZrO_2$ ceramic ferrule is manufactured by grinding process because the demands precision is very high. And the co-axle grinding process of $ZrO_2$ ceramic ferrule is to make its concentricity all of uniform before centerless grinding. When co-axle grinding of ferrule supported by two pin, pin chucking alignment accuracy is very important. This paper deals with the analysis of the chucking alignment experiment with parallel error on the micro feeding equipment. Thus, if possible be finding highly good the chucking alignment of two pin.

• The Journal of the Acoustical Society of Korea
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• v.21 no.3
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• pp.230-236
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• 2002

A study on architecture of new parallel interference canceller which can be applied for reverse link of next generation mobile communication system supporting multi-rate is performed on this paper. The proposed method adopts new algorithm which can be applied for multi-rate system to reduce multiple access interference (MAI) which cause performance degradation of CDMA system and limit of channel capacity. The proposed system is evaluated by simulation results under various conditions. As a result, performance enhancement is achieved compared to existing conventional interference cancellers. Although the amount of calculation is increased, we can find that the performance is improved generally.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.181-190
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• 2014

This paper reports a cognitive radio network architecture based on overloaded multicarrier direct sequence code division multiple access (O-MC-DS-CDMA). The O-MC-DSCDMA technique combines CDMA with a multicarrier modulation technique to overcome the channel fading effects. In this technique, secondary users are enabled to share the available bandwidth with the existing primary users. Two sets of orthogonal Gold codes are used to support the primary and secondary users simultaneously. The orthogonality between the spreading codes is lost due to the non-zero cross correlation between the codes and the timing synchronization error in the uplink transmission, which causes interference between primary and secondary users. This paper proposes two modified hybrid parallel/successive interference cancellation techniques for primary and secondary user base station receivers with multiple antennas to suppress the interference among users. Interference among the same group of users is cancelled by parallel interference cancellation and the interference among groups is cancelled using successive interference cancellation. The simulation results confirmed that the proposed modified interference cancellation techniques show better BER performance over conventional interference cancellation techniques.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.5
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• pp.97-103
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• 2010

There are many algorithms for 2D to 3D graphic conversion technology which have the high complexity and large scale of iterative computation. So in this paper propose parallel algorithm and high speed graphics accelerator architecture using Park's MAMS(Multiple Access Memory System) for Phong Shading, one of many 3D algorithms. The Proposed SIMD processor architecture is simulated by HDL and simulated and got 30 times faster result. It means any kinds of 3D algorithm can make parallel algorithm and accelerated by SIMD processor with Park's MAMS for real time processing.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.81-89
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• 2007

This paper presents a parallel distributed implementation of the GHT (generalized Hough transform) for the fast processing on the MPI-based PC cluster. We tried to achieve the higher speedup mainly by alleviating the communication overhead through the pipelined broadcast and accumulator array partition strategy and by time overlapping of the communication and the computation over entire process. Experimental results show that nearly linear speedup is reachable by the proposed method on the MPI-based PC clusters connected through 100Mbps Ethernet switch.