• International Journal of Contents
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• v.1 no.1
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• pp.50-58
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• 2005

Generally, multidimensional data such as image and spatial data require large amount of storage space. There is a limit to store and manage those large amounts of data in single workstation. If we manage the data on parallel computing environment which is being actively researched these days, we can get highly improved performance. In this paper, we propose a parallel multidimensional index structure that exploits the parallelism of the parallel computing environment. The proposed index structure is nP(processor)-nxmD(disk) architecture which is the hybrid type of nP-nD and 1P-nD. Its node structure in-creases fan-out and reduces the height of an index. Also, a range search algorithm that maximizes I/O parallelism is devised, and it is applied to k-nearest neighbor queries. Through various experiments, it is shown that the proposed method outperforms other parallel index structures.

• Journal of information and communication convergence engineering
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• v.11 no.4
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• pp.298-306
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• 2013

The scale invariant feature transform (SIFT) is an effective algorithm used in object recognition, panorama stitching, and image matching. However, due to its complexity, real-time processing is difficult to achieve with current software approaches. The increasing availability of parallel computers makes parallelizing these tasks an attractive approach. This paper proposes a novel parallel approach for SIFT algorithm implementation using a block filtering technique in a Gaussian convolution process on the SIMD Pixel Processor. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and input/output capabilities of the processor, which results in a system that can perform real-time image and video compression. We apply this implementation to images and measure the effectiveness of such an approach. Experimental simulation results indicate that the proposed method is capable of real-time applications, and the result of our parallel approach is outstanding in terms of the processing performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.3
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• pp.357-364
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• 2014

In this work, we construct a CPU cluster to implement a parallel finite-difference time domain(FDTD) algorithm for fast electromagnetic analyses. This parallel FDTD algorithm can reduce the computational time significantly and also analyze electrically larger structures, compared to a single FDTD counterpart. The parallel FDTD algorithm needs communication between neighboring processors, which is performed by the MPI(Message Passing Interface) library and a 3-D domain decomposition is employed to decrease the communication time between neighboring processors. Compared to a single-processor FDTD, the speed up factor of a-CPU-cluster-based parallel FDTD algorithm is investigated for the normal mode and the hypermode and finally analyze an electrically large concrete structure by the developed parallel algorithm.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.333-340
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• 2018

This paper introduces a BCH code decoder using parallel CRC(: Cyclic Redundancy Check) generation. Using a conventional parallel syndrome generator with a LFSR(: Linear Feedback Shift Register), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in $0.35-{\mu}m$ CMOS process.

• International Journal of Contents
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• v.1 no.1
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• pp.40-44
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• 2005

This paper introduces region partitioning method of non-perfect nested loops with non-uniform dependences. This kind of loop normally can't be parallelized by existing parallelizing compilers and transformations. Even when parallelized in rare instances, the performance is very poor. Based on the Convex Hull theory which has adequate information to handle non-uniform dependences, this paper proposes an enhanced region partitioning method which divides the iteration space into minimum parallel regions where all the iterations inside each parallel region can be executed in parallel by using variable renaming after copying.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2006.06a
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• pp.303-310
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• 2006

The sorting algorithms have been developed to take advantage of distributed computers. But the speedup of parallel sorting algorithms decrease rapidly with increased number of processors due to parallel processing overhead such as context switching time and inter-processor communication cost. In this paper, we propose a parallel sorting method which provides linear speedup of an optimal serial algorithm for a system with a large number of processors. This algorithm may even provide superlinear speedup for a practical system. The algorithm takes advantage of an interconnection network properties and its protocol.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1991.10a
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• pp.6-22
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• 1991

This thesis presents a parallel implementation of an iterative method for large scale, sparse linear system and gives result of computational experiments performed on both single transputer and multi transputer parallel computers. To solve linear system, we use conjugate gradient method and develope data storage techinique, data communication scheme. In addition to the explanation of conjugate gradient method, the result of computational experiment is summarized.

• Journal of Korea Society of Industrial Information Systems
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• v.3 no.1
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• pp.258-268
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• 1998

This paper presents two sequential advanced split and merge algorithms and a parallel image segmentation algorithm based on them. First, the two advanced methods are obtained from the combination of edge detection and classic split and merge to solve the inherent problems of the classical method. Besides, the parallel image segmentation algorithm on mesh-connected MIMD system considers three types in the merge stage to reduce the communication overhead between processors, such as intraprocessor merge, interprocessor with boundary merge, and interprocessor without boundary merge. Finally , we prove that the proposed algorithms achieve the improved performance by implementing them.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.233-236
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• 2001

Parallel operation scheme to several transformers is adopted because of the load increase, economic problem, or load shedding. For the transformer's parallel operation, loads proportional to each transformer's capacity must be allotted, and circulation currents must be limited as much as without causing any problem in a real operation. But, both transformers in parallel operation can be tripped when either faults at lower voltage side of a transformer or faults in a bus occurs. Therefore, parallel operation scheme to distribution transformers in Korea is not adopted in a normal state but only when loaded or load-shedded. These are due to the insufficiency of the construction in communication network and AVR scheme. Besides that, those are because bus bar protection scheme to lower voltage side of a transformer is not applied. In spite of enormous initial investment costs, advanced countries take so much account of power system reliability and stable supply that they adopt the parallel operation scheme in a normal state. One of the problems in parallel operation is the overheat of transformers due to the excessive circulation currents. This paper presents the scheme that controls voltages between both transformers using circulation currents that occurs in parallel operation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.277-278
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• 2005

Admittance Spectroscopic analysis was applied to study the effect of LiF buffer layer and to model the equivalent circuit for poly(2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylenevinylene) (MEH-PPV)-based polymer light emitting diodes (PLEDs) with the LiF cathode buffer layer. The single layer device with ITO/MEH-PPV/Al structure can be modeled as a simple parallel combination of resistor and capacitor. Insertion of a LiF layer at the Al/MEH-PPV interface shifts the highest occupied molecular orbital level and the vacuum level of the MEH-PPV layer as a result the barrier height for electron injection at the Al/MEH-PPV interface is reduced. The admittance spectroscopy measurement of the devices with the LiF cathode buffer layer shows reduction in contact resistance ($R_c$), parallel resistance ($R_p$) and increment in parallel capacitance ($C_p$).