• 제어로봇시스템학회:학술대회논문집
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• 1996.10a
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• pp.243-246
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• 1996

Modular robot manipulator is a robotic system assembled from discrete joints and links into one of many possible manipulator configurations. This paper describes the design method of newly developed modular robot manipulator and the methodology of a task based reconfiguration of it. New locking mechanism is proposed and it provides quick coupling and decoupling. A parallel connection method is devised and it makes modular robot manipulator working well and the number of components on each module reduced. To automatically determine a sufficient or optimal arrangement of the modules for a given task, we also devise an algorithm that automatically generates forward and inverse manipulator kinematics, and we propose an algorithm which maps task specifications to the optimized manipulator configurations. Efficient genetic algorithms are generated and used to search for a optimal manipulator from task specifications. A few of design examples are shown.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Proceedings of the Korean Information Science Society Conference
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• 2010.06c
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• pp.323-327
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• 2010

본 논문은 차분 진화 알고리즘의 최적해 탐색 능력을 향상시키기 위해 병렬 처리기법을 적용한 기법을 제안한다. 이를 위해서 기존의 개체군들을 5개의 그룹으로 나누어서 독립적으로 최적화 과정을 하도록 하여 일정한 확률에 의해서 각 그룹이 다른 그룹의 Best individual들을 변이 과정에서 참조하도록 하였다. 이러한 방식을 통해서 기존 차분 진화 알고리즘이 가지고 있는 지역해 수렴 문제를 해결하는 할 수 있도록 하였다. 실험을 통해서 제안된 차분 진화 알고리즘(P-DE)의 탐색 능력을 비교 및 분석 하였다. 실험 결과 제안된 차분 진화 알고리즘(P-DE)이 지역해 수렴 문제를 충분히 해결함으로써 기존의 알고리즘에 비해서 우수한 성능을 보이는 것을 확인 하였다.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.104-106
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• 2007

In this paper, we propose an approach to design of optimized Cascade controller for Rotary Inverted Pendulum system using Hierarchical Fair Competition-based Genetic Algorithm(HFCGA). GAs may get trapped in a sub-optimal region of the search space thus becoming unable to find better quality solutions, especially for very large search space. The Parallel Genetic Algorithms(PGA) are developed with the aid of global search and retard premature convergence. HFCGA is a kind of multi-populations of PGA. In this paper, we design optimized Cascade controller by HFCGA for Rotary Inverted Pendulum system that is nonlinear and unstable. Cascade controller comprise two feedback loop, parameters of controller optimize using HFCGA. Then designed controller evaluate by apply to the real plant.

• Journal of the Korean Operations Research and Management Science Society
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• v.37 no.3
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• pp.39-55
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• 2012

This paper presents an endosymbiotic evolutionary algorithm (EEA) to solve both problems of line balancing and model sequencing in a mixed-model two-sided assembly line (MMtAL) simultaneously. It is important to have a proper balancing and model sequencing for an efficient operation of MMtAL. EEA imitates the natural evolution process of endosymbionts, which is an extension of existing symbiotic evolutionary algorithms. It provides a proper balance between parallel search with the separated individuals representing partial solutions and integrated search with endosymbionts representing entire solutions. The strategy of localized coevolution and the concept of steady-state genetic algorithms are used to improve the search efficiency. The experimental results reveal that EEA is better than two compared symbiotic evolutionary algorithms as well as a traditional genetic algorithm in solution quality.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.5
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• pp.343-356
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• 1991

An efficient real-time implementation of digital filtering algorithms using a multiprocessor system in a ring network is investigated. The development time and cost for implementing a high speed signal processing system can be considerably reduced because algorithm are implemented in software using commercially available digital signal processors. This method is based on a parallel block processing approach, where a continuously supplied input data is divided into blocks, and the blocks are processed concurrently by being assigned to each processor in the system. This approach not only requires a simple interconnection network but also reduces the number of communications among the processors very much. The data dependency of the blocks to be processed concurrently brings on dependency problems between the processors in the system. A systematic scheduling method has been developed by using a processors which can be used efficiently, the methods for solving dependency problems between the processors are investigated. Implementation procedures and results for FIR, recursive (IIR), and adaptive filtering algorithms are illustrated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.761-764
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• 2013

Visiting k-combinations of a set S which has n elements is the general representation of many engineering problems. The performance of algorithms visiting all combinations, however, dramatically degrades with growing cases and the time to evaluate each combination. This paper presents the method to enhance the performance of these algorithms by a CUDA method. The experimental results show that the parallel algorithm running on GPU is approximately 900 times faster than the serial algorithm running on CPU.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.5
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• pp.97-103
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• 2010

There are many algorithms for 2D to 3D graphic conversion technology which have the high complexity and large scale of iterative computation. So in this paper propose parallel algorithm and high speed graphics accelerator architecture using Park's MAMS(Multiple Access Memory System) for Phong Shading, one of many 3D algorithms. The Proposed SIMD processor architecture is simulated by HDL and simulated and got 30 times faster result. It means any kinds of 3D algorithm can make parallel algorithm and accelerated by SIMD processor with Park's MAMS for real time processing.

• Journal of Mechanical Science and Technology
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• v.18 no.1
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• pp.30-36
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• 2004

In this paper, operation algorithms for a parallel HEV equipped with a relatively small motor are investigated. For the HEV, the power assist and the equivalent fuel algorithms are proposed. In the power assist algorithm, an electric motor is used to assist the engine which provides the primary power source. Tn the equivalent fuel algorithm, the electric energy stored in the battery is considered to be an equivalent fuel, and an equivalent brake specific fuel consumption for the electric energy is proposed. From the equivalent fuel algorithm, distribution of the engine power and the motor power is determined to minimize the fuel consumption for a given battery state of charge (SOC) and a required vehicle power. It is found from the simulation results that the fuel economy and the final battery SOC depend on the motor discharge energy and it is the best way to charge the battery only by the regenerative braking, not by the engine to improve the overall fuel efficiency of the HEV with the relatively small motor.

• Journal of electromagnetic engineering and science
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• v.6 no.3
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• pp.147-154
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• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.