• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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• pp.2395-2397
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• 2005

A low voltage operated piezoelectric RF MEMS in-line switch has been realized by using silicon bulk micromachining technologies for advanced mobile/wireless applications. The developed RF MEMS in-line switches were comprised of four piezoelectric cantilever actuators with an Au contact metal electrode and a suspended Au signal transmission line above the silicon substrate. The measured operation dc bias voltages were ranged from 2.5 to 4 volts by varying the thickness and the length of the piezoelectric cantilever actuators, which are well agreed with the simulation results. The measured isolation and insertion loss of the switch with series configuration were -43dB and -0.21dB (including parasitic effects of the silicon substrate) at a frequency of 2GHz and an actuation voltage of 3 volts.

• 마이크로전자및패키징학회지
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• 제7권2호
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• pp.47-53
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• 2000

TSM(Top Surface Metallurgy)이 증착된 유리기판의 Pb-free 솔더에 대한 젖음성을 무플럭스하에서 wetting balance법으로 평가하였다. TSM 층의 젖음성을 단면 증착시편의 wetting balance법으로부터 도출된 새로운 젖음성 지수들로 평가할 수 있었다. 유리기판의 TSM층으로는, Cu를 젖음층으로 하고 Au를 Cu의 산화 방지 층으로 사용하는 경우가 Au 자체를 젖음층으로 사용하는 경우보다 우수하였다. SnSb 솔더는 SnAg, SnBi, SnIn 솔더보다 TSM층에 대한 젖음특성이 우수하였다. 유리기판에 단면 증착된 TSM과 Pb-free솔더의 접촉각을 $F_{s}$와 기울어짐각을 측정하고, 메니스커스의 정적 상태에서 힘의 평형으로부터 유도된 식을 이용하여 계산할 수 있었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2007년도 SMT/PCB 기술세미나
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• pp.37-47
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• 2007

Factor : Structure Metal pad & SMO size Board level TC test : - Large SMO size better Board level Drop test : - Large SMO size better Factor : Structure Substrate thickness Board level TC test : - Thick substrate better Board level Drop test : - Substrate thickness is not a significant factor for drop test Factor : Material Solder alloy Board level TC test : - Not so big differences over Pb-free solder and NiAu, OSP finish Board level Drop test : - Ni/Au+SAC105, CuOSP+LF35 are better Factor : Material Pad finish Board level TC test : - NiAu/NiAu is best Board livel Drop test : - CuOSP is best Factor : Material Underfill Board level TC test - Several underfills (reworkable) are passed TCG x500 cycles Board level Drop test : - Underfill lots have better performance than non-underfill lots Factor : Process Multiple reflow Board level TC test : - Multiple reflow is not a significant actor for TC test Board level Drop test : N/A Factor : Process Peak temp Board level TC test : - Higher peak temperature is worse than STD Board level Drop test : N/A Factor : Process Stack method Board level TC test : - No big difference between pre-stack and SMT stack Board level Drop test : - Flux dipping is better than paste dipping but failure rate is more faster

• 마이크로전자및패키징학회지
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• 제22권2호
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• pp.41-45
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• 2015

리드프레임의 우수한 열적/전기적 특성을 유지하면서 많은 I/O수를 수용할 수 있는 구조, 그리고 라미네이트의 디자인 팬인(Fan-in) 및 팬아웃(Fan-out) 설계 유연성을 유지하면서 가격경쟁력을 향상 시킬 수 있는 몰딩기판(Molded substrate)을 기반으로 한 RtMLF(Routable Molded Lead Frame) 패키지를 개발하였다. 개발된 패키지의 구조적 특징을 이용하여, 열적 전기적 성능의 우수성을 시뮬레이션을 통해서 확인하였으며, 제조 및 신뢰성 분석을 수행하여 생산 적용 가능성을 확인하였다.

• 마이크로전자및패키징학회지
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• 제21권1호
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• pp.13-17
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• 2014

The direct-patternable $SnO_2$ thin film was successfully fabricated by photochemical metal-organic deposition. The composition and chemical bonding state of $SnO_2$ thin film were analyzed by using X-ray photoelectron spectroscopy (XPS) from the surface to the interface with Si substrate. XPS depth profiling analysis allowed the determination of the atomic composition in $SnO_2$ film as a function of depth through the evolution of four elements of C 1s, Si 2p, Sn 3d, and O 1s core level peaks. At the top surface, nearly stoichiometric $SnO_2$ composition (O/Sn ratio is 1.92.) was observed due to surface oxidation but deficiency of oxygen was increased to the interface of patterned $SnO_2/Si$ substrate where the O/Sn ratio was about 1.73~1.75 at the films. This O deficient state of the film may act as an n-type semiconductor and allow $SnO_2$ to be applied as a transparent electrode in optoelectronic applications.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.65-68
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• 2013

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process. A selective solder bumping mechanism without the mask is based on the material design of SBM. Maskless screen printing process can implement easily a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology. Its another advantage is ternary or quaternary lead-free SoP can be formed easily. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 ${\mu}m$ is, successfully, formed.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.151-155
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• 2003

The requirements for harsh environment electronic controllers in automotive applications have been steadily becoming more and more stringent. Electronic substrate technologists have been responding to this challenge effectively in an effort to meet the performance, reliability and cost requirements. An effect of the plasma cleaning at the alumina substrate and the IMC layer between $Sn-37wt\%Pb$ solder and Ag-Pd thick film conductor after reflow soldering has been studied. Organic residual carbon layer was removed by the substrate plasma cleaning. So the interfacial adhesive strength was enhanced. As a result of AFM measurement, Ag-Pd conductor pad roughness were increased from 304nm to 330nm. $Cu_6Sn_5$ formed during initial ref]ow process at the interface between TiWN/Cu UBM and solder grew by the succeeding reflow process so the grains had a large diameter and dense interval. A cellular-shaped $Ag_3Sn$ was observed at the interface between Ag-Pd conductor pad and solder. The diameters of the $Ag_3Sn$ grains ranged from about $0.1\~0.6{\mu}m$. And a needle-shaped $Ag_3Sn$ was also observed at the inside of the solder.

• 마이크로전자및패키징학회지
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• 제7권3호
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• pp.27-29
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• 2000

Lift-off를 이용한 DLC-coated Si-tip FEA 제조에 있어서 gate 절연막의 측면에 DLC가 coating되는 것을 방지하기 위해 기판 상에 Al 희생층을 경사-회전 증착한 뒤 DLC를 coating하고, 다음으로 희생층을 식각하여 tip 이외의 DLC를 제거하는 방법을 제안하였다. 이러한 Al희생층을 이용한 lift-off공정에 의해 제조된 DLC-coated Si-tip FEA의 전류전압 특성과 전류 표동 특성을 조사하였으며, gate 누설 전류의 감소와 방출 전류의 안정성을 확인하였다.

• 마이크로전자및패키징학회지
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• 제9권3호
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• pp.31-36
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• 2002

PBGA에 비해 상대적으로 큰 칩을 실장하는 고속 SRAM용 153 FC-BGA을 대상으로 2차 솔더접합부의 신뢰성을 평가하였다. 실험은 열사이클 시험에서 발생하는 단면과 양면 실장, 패키지 구조, 언더 필 재료, 기판의 종류와 두께, 솔더 볼의 크기에 따른 영향을 분석하였다. BT기판의 두께가 0.95mm에서 1.20mm로 증가하고, 낮은 영률 의 언더 필 재료에서 솔더접합부의 피로 수명이 30% 향상됨을 확인하였다. 또한 솔더 볼의 크기가 0.76 mm에서 0.89mm로 증가하면, 솔더접합부에서 균열에 대한 저항성은 2배 정도 증가하였다.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.53-58
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• 2013

An innovative packaging solution, Flip Chip with Copper (Cu) Column bond on lead (BOL) Enhanced Process (fcCuBE$^{(R)}$) delivers a cost effective, high performance packaging solution over typical bond on capture pad (BOC) technology. These advantages include improved routing efficiency on the substrate top layer thus allowing conversion functionality; furthermore, package cost is lowered by means of reduced substrate layer count and removal of solder on pad (SOP). On the other hand, as electronic packaging technology develops to meet the miniaturization trend from consumer demand, reliability testing will become an important issue in advanced technology area. In particular, electromigration (EM) of flip chip bumps is an increasing reliability concern in the manufacturing of integrated circuit (IC) components and electronic systems. This paper presents the results on EM characteristics on BOL and BOC structures under electrical current stressing in order to investigate the comparison between two different typed structures. EM data was collected for over 7000 hours under accelerated conditions (temperatures: $125^{\circ}C$, $135^{\circ}C$, and $150^{\circ}C$ and stress current: 300 mA, 400 mA, and 500 mA). All samples have been tested without any failures, however, we attempted to find morphologies induced by EM effects through cross-sectional analysis and investigated the interfacial reaction characteristics between BOL and BOC structures under current stressing. EM damage was observed at the solder joint of BOC structure but the BOL structure did not show any damage from the effects of EM. The EM data indicates that the fcCuBE$^{(R)}$ BOL Cu column bump provides a significantly better EM reliability.