• Journal of the Korean Geotechnical Society
• /
• v.27 no.7
• /
• pp.47-57
• /
• 2011

The p-y curve has been used to design pile foundations subjected to lateral loading. Although the p-y curve has a large influence on the pile lateral behavior, p-y curves have not been clearly suggested. In this study, the p-y curve of clay was evaluated for drilled shafts in marine deposits by using 3-dimensional numerical analyses. First, the optimization study was performed to properly determine boundary extent, mesh size, and interface stiffness. The numerical modeling in the study was verified by comparing the calculated and the pile loading test results. Then, the p-y curves of single and group piles were evaluated from the parametric study. The selected parameters were pile diameter, pile Young's modulus and pile head fixed condition for a single pile, and pile spacing for group piles. Finally, the p-multiplier was evaluated by comparing the p-y curves of a single pile and group piles. As a result, the p-multiplier at pile spacing of 3D was 0.83, 0.67 and 0.78 for the front, middle, and back row piles, respectively, and showed values similar to those of O'Neill and Reese (1999). For the pile group with pile spacing larger than 60, the group effect can be ignorable.

• Journal of the Chungcheong Mathematical Society
• /
• v.29 no.4
• /
• pp.613-629
• /
• 2016

In this paper, we introduced the notion of multiplier of Boolean algebras and discuss related properties between multipliers and special mappings, like dual closures, homomorphisms on B. We introduce the notions of xed set $Fix_f(X)$ and normal ideal and obtain interconnection between multipliers and $Fix_f(B)$. Also, we introduce the special multiplier ${\alpha}_p$a nd study some properties. Finally, we show that if B is a Boolean algebra, then the set of all multipliers of B is also a Boolean algebra.

• Kyungpook Mathematical Journal
• /
• v.46 no.1
• /
• pp.97-109
• /
• 2006

In this paper, the authors introduce new classes of p-valent functions defined by Dziok-Srivastava linear operator and the multiplier transformation and study their properties by using certain first order differential subordination and superordination. Also certain inclusion relations are established and an integral transform is discussed.

• Journal of the Korean GEO-environmental Society
• /
• v.10 no.5
• /
• pp.69-73
• /
• 2009

In this study, three dimensional numerical analyses were performed with variation of pile spacing (S=3D, 4D, 5D) to compare the behaviour of single pile and pile group with cap in granite soil. In order to compare and analyze the lateral resistance of single pile and pile group by changing pile spacing, the pile group with array of $1{\times}3$ was employed. To reduce the computation time the symmetric boundary condition was used. And Druker-Prager model and elasticity model were used for granite soil and for concrete pile and cap, respectively. Using the analyses results of pile group in granite soil under lateral loading, p-y curve for pile group and single pile with changing pile spacing was drawn. With p-y curve p-multiplier was evaluated. As a result of analysis, the value of p-multiplier was increased with increasing pile spacing under 1.0 due to pile shadow effects.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.18 no.3
• /
• pp.33-44
• /
• 2008

The efficiency of pairing based cryptosystems depends on the computation of pairings. pairings is defined over finite fileds GF$(3^m)$ by trinomials due to efficiency. The hardware architectures for pairings have been widely studied. This paper proposes new adder and multiplier for GF(3) which are more efficient than previous results. Furthermore, this paper proposes a new unified adder-subtractor for GF$(3^m)$ based on the proposed adder and multiplier. Finally, this paper proposes new multiplier for GF$(3^m)$. The proposed MSB-first bit-serial multiplier for GF$(p^m)$ reduces the time delay by approximately 30 % and the size of register by half than previous LSB-first multipliers. The proposed multiplier can be applied to all finite fields defined by trinomials.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.205-208
• /
• 2000

In this paper, a low voltage CMOS analog four-quadrant multiplier using two V-I converters is presented. The proposed V-I converter is composed of the series composite transistor and the low voltage composite transistor. The designed analog four-quadrant multiplier has simulated by HSPICE using 0.25$\mu\textrm{m}$ n-well CMOS process parameters with a 2V supply voltage. Simulation results show that the power dissipation is 1.55㎿, the cutoff frequency is 489MHz, and the THD can be 0.26％ at maximum differential input of 1V$\sub$p-p/.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.318-321
• /
• 2000

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fie2, degree of uk terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for perform above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesize ${\alpha}$$\^$k/ generation module and control signal CSt generation module with A-cell and M-cell. Then, we propose the future research and prospects.

• Communications of the Korean Mathematical Society
• /
• v.16 no.2
• /
• pp.205-210
• /
• 2001

In this paper we will determine Schur multipliers of some finite p-groups of order p$^4$.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.3C
• /
• pp.176-184
• /
• 2005

In this paper, we implemented an Elliptic Curve Cryptography(ECC) processor for Digital Transmission Contents Protection (DTCP), which is a standard for protecting various digital contents in the network. Unlikely to other applications, DTCP uses ECC algorithm which is defined over GF(p), where p is a 160-bit prime integer. The core arithmetic operation of ECC is a scalar multiplication, and it involves large amount of very long integer modular multiplications and additions. In this paper, the modular multiplier was designed using the well-known Montgomery algorithm which was implemented with CSA(Carry-save Adder) and 4-level CLA(Carry-lookahead Adder). Our new ECC processor has been synthesized using Samsung 0.18 m CMOS standard cell library, and the maximum operation frequency was estimated 98 MHz, with the size about 65,000 gates. The resulting performance was 29.6 kbps, that is, it took 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption and decryption, and key exchanges in real time environments.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.24 no.6
• /
• pp.736-743
• /
• 2020

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.