• Asian-Australasian Journal of Animal Sciences
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• v.27 no.1
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• pp.131-139
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• 2014

This study was performed to determine the effect of dietary supplementation of procyanidin on growth performance, blood characteristics, and immune function in growing pigs. In experiment 1 (Exp. 1), thirty-two crossbred pigs with an initial BW of $19.2{\pm}0.3$ kg were allocated into 4 treatments for an 8-wk experiment: i) CON (basal diet), ii) MOS 0.1 (basal diet+0.1% mannanoligosaccharide), iii) Pro-1 (basal diet+0.01% procyanidin), and iv) Pro-2 (basal diet+0.02% procyanidin). Pigs fed Pro-1 and Pro-2 diets had greater (p<0.05) gain:feed ratio compared with those fed CON or MOS 0.1 diets. Serum creatinine concentration was less (p<0.05) in Pro-2 treatment than those in CON, MOS 0.1 and Pro-1 treatments. In Exp. 2, twelve pigs (BW $13.4{\pm}1.3$ kg) received basal diet with i) 0 (CON), ii) 0.02% (Pro-0.02%), and iii) 0.04% procyanidin (Pro-0.04%) for 4 wk. Concentration of platelets was lower (p<0.05) in the Pro-0.04% group compared to CON at 24 h after lipopolysaccharide (LPS) challenge. In addition, secretion of cytokines from cultured peripheral blood mononuclear cells (PBMC) in the presence or absence of procyanidin was examined. The levels of interleukin (IL)-$1{\beta}$, IL-6 and tumor necrosis factor (TNF)-${\alpha}$ were lower (p<0.05) in Pro (LPS-stimulated PBMCs+procyanidin) than those in CON (LPS-stimulated PBMCs+PBS) at 4 h after LPS challenge. These data suggest that dietary addition of procyanidin improves feed efficiency and anti-inflammatory cytokines of pigs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.8-9
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• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.102-111
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• 1989

In this paper two new non-inverting type BiCMOS drivers are proposed. These are characterized by the use of pMOSFET's in charging the bases of pull-down bipolar transistors. The delay time in pull-up transition of the proposed drivers is 20%-47% shorter than that of the drivers of current using. The proposed drivers use 1-3 fewer MOSFET's in comparison with the drivers of current using.

• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• The Journal of the Acoustical Society of Korea
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• v.28 no.2E
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• pp.35-42
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• 2009

In this paper, we present criteria of objective measurement of speech quality to provide the mobile-VoIP services efficiently over wireless mobile internet. The mobile-VoIP service, which is based on mobility and is error-prone compared to conventional VoIP over wired network, is about to be launched, but there have not been adequate quality indexes and the Quality of Service (QoS) standards for evaluating speech quality of Mobile-VoIP. In addition, there are many factors influencing on the speech quality in packet network of which packet loss contribute directly to the overall voice communication quality. For this reason, we adopt the Gilbert-Elliot Channel Model for modeling packet network based on IP and assess the voice quality through the objective speech method of ITU-T P. 862 PESQ and ITU-T P. 862.1 MOS-LQO under various packet loss rates in the transmission channel environments. Our simulation results address the specific criteria and QoS for the mobile-VoIP services in terms of the various packet loss environments.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.123-123
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• 2000

선폭이 초미세화됨에 따라 게이트 전극에서의 공핍 현상 및 불순물 확산의 물제를 갖는 poly-Si 게이트를 대체할 전극 물질로 텅스텐(W)이 많이 연구되어 왔다. 반도체 소자의 배선물질로 일찍부터 사용되어온 텅스텐은 내화성 금속의 일종으로 용융점이 높고, 저항이 낮다. 그러나, 일반적으로 사용되고 있는 CVD에 의한 텅스텐의 증착은 반응가스(WF6)로부터 오는 불소(F)의 게이트 산화막내로의 확산으로 인해 MOS 소자가 크게 열화될수 있다. 본 연구에서는 W/TiN 이중 게이트 전극 구조를 갖는 MOS 캐패시터를 제작하여 전기적 특성을 살펴보았다. P-Type (100) Si위에 RTP를 이용, 85$0^{\circ}C$에서 110 의 열산화막을 성장 및 POA를 수행한 후, 반응성 스퍼터링법에 의해 상온, 6mTorr, N2/Ar=1/6 sccm, 100W 조건에서 TiN 박막을 150, 300, 500 의 3그룹으로 증착하였다. 그 위에 LPCVD 방법으로 35$0^{\circ}C$, 0.7Torr, WF6/SiH4/H2=5/5~10/500sccm 조건에서 2000~3000 의 텅스텐을 증착하였다. Photolithography 공정 및 습식 에칭을 통해 200$\mu\textrm{m}$$\times$200$\mu\textrm{m}$ 크기의 W/TiN 복층 게이트 MOSC를 제작하였다. W/TiN 복측 게이트 소자와 비교분석하기 위해 같은 조건의 산화막을 이용한 알루미늄(Al) 게이트, 텅스텐 게이트 MOSC를 제작하였다. 35$0^{\circ}C$에서 증착된 텅스텐 박막은 10~11$\Omega$/ 의 면저항을 가졌고 미소한 W(110) peak값을 나타내는 것으로 보아 비정질 상태에 가까웠다. TiN 박막의 경우 120~130$\Omega$/ 의 면저항을 가졌고 TiN (200)의 peak 값이 크게 나타난 반면, TiN(111) peak가 미소하게 나타났다. TiN 박막의 두께와 WF/SiH4의 가스비를 변화시켜가며 제작된 MOS 캐패시터를 HF 및 QS C-V, I-V 그리고 FNT를 통한 전자주입 방법을 이용하여 TiN 박막의 불소에 대한 확산 방지막 역할을 살펴 보았다. W/TiN 게이트 MOS 소자는 모두 순수 텅스텐 게이트보다 우수하였고, Al 게이트와 유사한 전기적 특성을 보여주었다. W/TiN 게이트 MOS 소자는 모두 순수 텅스텐 게이트보다 우수하였고, Al 게이트와 유사한 전기적 특성을 보여주었다. TiN 박막이 300 , 500 이고 WF6/SiH4의 가스비가 5:10인 경우 소자 특성이 우수하였으나, 5:5의 경우에는 FNT 전자주입 특성이 열화되기 시작하였다. 그리고, TiN박막의 두께가 150 으로 얇아질 경우에는 WF6/SiH4의 가스비가 5:10인 경우에서도 소자 특성이 열화되기 시작하였다. W/TiN 복층 게이트 MOS 캐패시터를 제작하여 전기적인 특성 분석결과, 순수 텅스텐 게이트 소자의 큰 저전계 누설 전류 특성을 해결할 수 있었으며, 불소확산에 영향을 주는 조건이 WF6/SiH4의 가스비에 크게 의존됨을 알 수 있었다. TiN 박막의 증착 공정이 최적화 될 경우, 0.1$\mu\textrm{m}$이하의 초미세소자용 게이트 전극으로서 텅스텐의 사용이 가능할 것으로 보여진다.

• Korean Journal of Psychosomatic Medicine
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• v.20 no.1
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• pp.59-65
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• 2012

Objectives : The present study takes part of the agricultural district cohort study of a certain county located in Gyeonggido and aims to investigate the difference of the heart rate variability(HRV) according to the social support level. Methods : We used data from 1727 participants of a health promotion program who are older than 40 years old. A physical examination, as well as a one-to-one interview to obtain sociodemographic characteristics, was performed with each participant. In addition, the participants completed the Medical Outcomes Study-Social Support Survey(MOS-SSS) for their the social support level to be assessed, and their HRV were measured to evaluate their autonomic function. The entire group was divided in two groups according to its MOS-SSS points to facilitate the research. Those who were evaluated as the high 25%(432 persons) were denominated as high social support (HSS) group and those who were evaluated as the low 25%(425 persons) were denominated as poor social support(PSS) group. Results : The two groups showed significant differences on the sociodemographic factor such as mean age and gender composition(p<0.05). Comparing the indices related to the HRV, the HSS group had the following values higher than the PSS group : SDNN(F=4.938, p=0.027), TP(F=8.088, p=0.005), VLF(F=6.220, p=0.013) LF (F=3.873, p=0.049). Conclusion : According to the research, the PSS group showed dysfunction on their autonomic nervous system comparing to the HSS group. The social support helps an individual overcome difficulties, helps the adaptation during the changes of circumstances and in stressful situations it serves like a buffer. Based on that, it's possible to define that a low social support level gave an impact on the autonomic function. Also, using the fact that the HRV can evaluate the autonomic function in an objective view, it was possible to visualize that it has a potential to be used as an assistant factor to evaluate the social support.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.339-339
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• 2012

현재 MOS 소자에 사용되고 있는 $SiO_2$ 산화막은 그 두께가 얇아짐에 따라 Gate Leakage current와 여러 가지 신뢰성 문제가 대두되고 있고, 이를 극복하고자 High-k물질을 사용하여 기존에 발생했던 Gate Leakage current와 신뢰성 문제를 해결하고자 하고 있다. 본 실험에서는 High-k(hafnium) Gate Material에 온도 변화를 주었을 때 여러 가지 전기적인 특성 변화를 보는 방향으로 연구를 진행하였다. 기본적인 P-Type Si기판을 가지고, 그 위에 있는 자연적으로 형성된 산화막을 제거한 후 Hafnium Gate Oxide를 Atomic Layer Deposition (ALD)를 이용하여 증착하고, Aluminium을 전극으로 하는 MOS-Cap 구조를 제작한 후 FGA 공정을 진행하였다. 마지막으로 $300^{\circ}C$, $450^{\circ}C$로 30분정도씩 Annealing을 하여, 온도 조건이 다른 3가지 종류의 샘플을 준비하였다. 3가지 샘플에 대해서 각각 I-V (Gate Leakage Current), C-V (Mobile Charge), Interface State Density를 분석하였다. 그 결과 Annealing 온도가 올라가면 Leakage Current와 Dit(Interface State Density)는 감소하고, Mobile Charge가 증가하는 것을 확인할 수가 있었다. 본 연구는 향후 High-k 물질에 대한 공정 과정에서의 다양한 열처리에 따른 전기적 특성의 변화 대한 정보를 제시하여, 향후 공정 과정의 열처리에 대한 방향을 잡는데 도움이 될 것이라 판단된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.163-166
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• 2002

We investigated structural and electrical properties of Metal-Oxide-Semiconductor(MOS) structure using Hafnium $oxide(HfO_{2})$ as high-k gate dielectric material. $HfO_{2}$ films are ultrathin gate dielectric material witch have a thickness less than 2.0nm， so it is spotlighted to be substituted $SiO_{2}$ as gate dielectric material. In this paper We have grown $HfO_{2}$ films with pt electrode on P-type Silicon substrate by RF magnetron sputtering system using $HfO_{2}$ target and oserved the property of semiconductor-oxide interface. Using pt electrode, it is necessary to be annealed at ${300^{\circ}C}$. This process is to increase an adhesion ratio between $HfO_{2}$ films with pt electrode. In film deposition process, the deposition time of $HfO_{2}$ films is an important parameter. Structura1 properties are invetigated by AES depth profile, and electrical properties by Capacitance-Voltage characteristic. Interface trap density are measured to observe the interface between $HfO_{2}$ with Si using High-frequency(1MHz) C-V and Quasi - static C-V characteristic.