• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.5-5
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• 2009

Thin-film-transistors (TFTs) that can be prepared at low temperatures have attracted much attention because of the great potential for transparent and flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited due to low field-effect mobility and rapid degradation after exposing to air. Alternative approach is the use of amorphous oxide semiconductors as a channel. Amorphous oxide semiconductors (AOSs) based TFTs showed the fast technological development, because AOS films can be fabricated at room temperature and exhibit the possibility in application like flexible display, electronic paper, and larges solar cells. Among the various AOSs, a-IGZO has lots of advantages because it has high channel mobility, uniform surface roughness and good transparency. [1] The high mobility is attributed to the overlap of spherical s-orbital of the heavy post-transition metal cations. This study demonstrated the effect of the variation in channel thickness from 30nm to 200nm on the TFT device performance. When the thickness was increased, turn-on voltage and subthreshold swing was decreased. The a-IGZO channels and source/drain metals were deposited with shadow mask. The a-IGZO channel layer was deposited on $SiO_2$/p-Si substrates by RF magnetron sputtering, where RF power is 150W. And working pressure is 3m Torr, at $O_2/Ar$ (2/28 sccm) atmosphere. The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. Finally, Al (150nm) as a gate metal was thermal-evaporated. TFT devices were heat-treated in a furnace at 250 $^{\circ}C$ and nitrogen atmosphere for 1hour. The electrical properties of the TFTs were measured using a probe-station. The TFT with channel thickness of 150nm exhibits a good subthreshold swing (SS) of 0.72 V/decade and on-off ratio of $1{\times}10^8$. The field effect mobility and threshold voltage were evaluated as 7.2 and 8 V, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.137-137
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• 2009

Thin-film transistors (TFTs) that can be prepared at low temperatures have attracted much attention due to the great potential for flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited by low field effect mobility or rapidly degraded after exposing to air in many cases. Another approach is amorphous oxide semiconductors. Amorphous oxide semiconductors (AOSs) have exactly attracted considerable attention because AOSs were fabricated at room temperature and used lots of application such as flexible display, electronic paper, large solar cells. Among the various AOSs, a-IGZO was considerable material because it has high mobility and uniform surface and good transparent. The high mobility is attributed to the result of the overlap of spherical s-orbital of the heavy pest-transition metal cations. This study is demonstrated the effect of thickness channel layer from 30nm to 200nm. when the thickness was increased, turn on voltage and subthreshold swing were decreased. a-IGZO TFTs have used a shadow mask to deposit channel and source/drain(S/D). a-IGZO were deposited on SiO2 wafer by rf magnetron sputtering. using power is 150W, working pressure is 3m Torr, and an O2/Ar(2/28 SCCM) atmosphere at room temperature. The electrodes were formed with Electron-beam evaporated Ti(30nm) and Au(70nm) structure. Finally, Al(150nm) as a gate metal was evaporated. TFT devices were heat treated in a furnace at $250^{\circ}C$ in nitrogen atmosphere for an hour. The electrical properties of the TFTs were measured using a probe-station to measure I-V characteristic. TFT whose thickness was 150nm exhibits a good subthreshold swing(S) of 0.72 V/decade and high on-off ratio of 1E+08. Field effect mobility, saturation effect mobility, and threshold voltage were evaluated 7.2, 5.8, 8V respectively.

• Journal of the Korean Electrochemical Society
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• v.14 no.1
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• pp.1-8
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• 2011

Ionic liquids are room-temperature molten salts, composed of organic mostly of organic ions that may undergo almost unlimited structural variation. We approach the new aspects of ionic liquids in applications where the semiconductor nanoparticles used as sensitizers of solar cells. We studied the effects of ionic liquids as capping ligand and/or solvent, on the morphology and phase of the CdSe/ZnS nanoparticles. Colloidal CdSe/ZnS nanoparticles were synthesized using a series of imidazolium ionic liquids; 1-R-3-methylimidazolium bis(trifluoromethylsulfonyl) imide ([RMIM][TFSI]), where R = ethyl ([EMIM]), butyl ([BMIM]), hexyl ([HMIM]), octyl ([OMIM]). The average size of nanoparticles was 8~9 nm, and both zinc-blende and wurtzite phase was produced. We also synthesized the nanoparticles using a mixture of trihexyltetradecylphosphonium bis(trifluoromethylsulfonyl)imide ([$P_{6,6,6,14}$][TFSI]) and octadecene (ODE). The CdSe/ZnS nanoparticles have a smaller size (5.5 nm) than that synthesized using imidazolium, and with a controlled phase from zinc-blende to wurtzite by increasing the volume ratio of [$P_{6,6,6,14}$][TFSI]. For the first time, the phase and size control of the CdSe/ZnS nanoparticles was successfully demonstrated using those ionic liquids.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.180-180
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• 2012

Heteroepitaxial GaN nano- and micro-rods (NMRs) are one of the most promising structures for high performance optoelectronic devices such as light emitting diodes, lasers, solar cells integrated with Si-based electric circuits due to their low dislocation density and high surface to volume ratio. However, heteroepitaxial GaN NMRs growth using a metal-organic vapor phase epitaxy (MOVPE) machine is not easy due to their long surface diffusion length at high growth temperature of MOVPE above $1000^{\circ}C$. Recently some research groups reported the fabrication of the heteroepitaxial GaN NMRs by using MOVPE with vapor-liquid-solid (VLS) technique assisted by metal catalyst. However, in the case of the VLS technique, metal catalysts may act as impurities, and the GaN NMRs produced in this mathod have poor directionallity. We have successfully grown the vertically well aligned GaN NMRs on Si (111) substrate by means of self-catalystic growth methods with pulsed-flow injection of precursors. To grow the GaN NMRs with high aspect ratio, we veried the growth conditions such as the growth temperature, reactor pressure, and V/III molar ratio. We confirmed that the surface morphology of GaN was strongly influenced by the surface diffusion of Ga and N adatoms related to the surrounding environment during growth, and we carried out theoretical studies about the relation between the reactor pressure and the growth rate of GaN NMRs. From these results, we successfully explained the growth mechanism of catalyst-free and mask-free heteroepitaxial GaN NMRs on Si (111) substrates. Detailed experimental results will be discussed.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.151-151
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• 2013

무기물 기반, Si-based 태양전지에 비해 가볍고 저렴하다는 관점에서 유기태양전지에 대한 연구가 진행되고 있다. 유기태양전지는 Si-based 태양전지에 비해 그 효율이 낮다는 점이 문제로 제기되어 왔지만, 억셉터와 도너의 nanocomposite 구조인 bulk-heterojunction (BHJ) 구조가 개발이 되면서 유기물의 짧은 엑시톤(exciton) 거리를 극복할 수 있게 되어 그 효율이 비약적으로 증가되는 결과를 낳았다. 또한 넓은 범위의 파장을 흡수 할 수 있는 작은 band-gap을 갖는 물질이 개발됨으로써 유기 태양전지의 효율은 점차 증가하고 있다. 최근에는 독일 회사인 Heliatek에서 12%가 넘는 유기태양전지를 발표함으로써 유기태양전지가 Si-based 태양전지를 대체할 수 있는 차세대 에너지 공급원으로의 가능성을 충분히 보였다. 이런 유기 태양전지는 하부 투명전극인 인듐주석산화물(ITO)/정공이동층(PEDOT:PSS)/광흡수층/전자이동층(LiF)/낮은 일함수를 갖는 상부전극인 Al 구조의 일반적인 구조; ITO/전자이동층/광흡수층/정공이동층/높은 일함수를 갖는 상부전극(Ag), 전하의 이동방향이 반대인 역구조 태양전지, 두 가지로 분류할 수 있다. 하지만 소자 안정성의 관점에서 일반적인 구조의 태양전지는 ITO/PEDOT:PSS 계면에서의 화학적 불안정성과, 낮을 일함수를 갖는 상부전극이 쉽게 산화되는 등의 문제가 있어 상부전극으로 높은 일함수를 갖는 전극을 사용하는 역구조 태양전지가 더 유리하다. 이러한 역구조 태양전지에서 효율을 높일 수 있는 요인 중 하나는 전자이동층에 있다. 광흡수층에서 형성되어 분리된 전자가 전극으로 이동하기위해서는 전자이동층을 거쳐야 한다. 하지만 이 전자이동층 내에서의 전자 이동속도가 느리다면, 즉 저항이 크다면 광흡수증과의 계면에서 Back electron trasnfer현상으로 재결합이 일어나게 되어 전극으로 도달하는 전자의 양이 줄어들게 되고, 이는 유기태양전지 효율을 낮추는 요인이 된다. 전자이동층 자체의 저항뿐만 아니라, 전자이동층의 표면 거칠기(morphology) 또한 유기 태양전지의 효율을 좌우하는 요인 중 하나이다. 광흡수층과 전자이동층의 계면에서 전자의 이동이 일어나는데, 전자이동층의 표면 거칠기가 크게되면 그 위에 박막으로 형성되는 광흡수층과의 계면저항이 증가하게 되고, 이는 광흡수층에서 전자이동층으로의 원활한 전자이동을 저해함으로써 소자 효율의 감소를 일으키게 된다. 따라서 우리는 전자이동층인 ZnO 박막의 스퍼터링 조건을 변화시킴으로써 ZnO 층의 두께에 따른 광투과도, 전기전도성 변화 및 유기태양전지의 효율변화와, 표면 거칠기에 따른 광변환 효율 변화를 관찰하고자 한다.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.