• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.375-375
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• 2010

CdTe as an absorber material is widely used in thin film solar cells with the heterostructure due to its almost ideal band gap energy of 1.45 eV, high photovoltaic conversion efficiency, low cost and stable performance. The deposition methods and preparation conditions for the fabrication of CdTe are very important for the achievement of high solar cell conversion efficiency. There are some rearranged reports about the deposition methods available for the preparation of CdTe thin films such as close spaced sublimation (CSS), physical vapor deposition (PVD), vacuum evaporation, vapor transport deposition (VTD), closed space vapor transport, electrodeposition, screen printing, spray pyrolysis, metalorganic chemical vapor deposition (MOCVD), and RF sputtering. The RF sputtering method for the preparation of CdTe thin films has important advantages in that the thin films can be prepared at low growth temperatures with large-area deposition suitable for mass-production. The authors reported that the optical and electrical properties of CdTe thin film were closely connected by the thickness-uniformity of the film in the previous study [1], which means that the better optical absorbance and the higher carrier concentration could be obtained in the better condition of thickness-uniformity for CdTe thin film. The thickness-uniformity could be controlled and improved by the some process parameters such as vacuum level and RF power in the sputtering process of CdTe thin films. However, there is a limitation to improve the thickness-uniformity only in the preparation process [1]. So it is necessary to introduce the external or additional method for improving the thickness-uniformity of CdTe thin film because the cell size of thin film solar cell will be enlarged. Therefore, the authors firstly applied the chemical mechanical polishing (CMP) process to improving the thickness-uniformity of CdTe thin films with a G&P POLI-450 CMP polisher [2]. CMP process is the most important process in semiconductor manufacturing processes in order to planarize the surface of the wafer even over 300 mm and to form the copper interconnects with damascene process. Some important CMP characteristics for CdTe were obtained including removal rate (RR), WIWNU%, RMS roughness, and peak-to-valley roughness [2]. With these important results, the CMP process for CdTe thin films was performed to improve the thickness-uniformity of the sputtering-deposited CdTe thin film which had the worst two thickness-uniformities of them. Some optical properties including optical transmittance and absorbance of the CdTe thin films were measured by using a UV-Visible spectrophotometer (Varian Techtron, Cary500scan) in the range of 400 - 800 nm. After CMP process, the thickness-uniformities became better than that of the best condition in the previous sputtering process of CdTe thin films. Consequently, the optical properties were directly affected by the thickness-uniformity of CdTe thin film. The absorbance of CdTe thin films was improved although the thickness of CdTe thin film was not changed.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.308-309
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• 2012

One of the critical issues in the growth of multijunction solar cell is the formation of a highly doped Esaki interband tunnel diode which interconnects unit cells of different energy band gap. Small electrical and optical losses are the requirements of such tunnel diodes [1]. To satisfy these requirements, tens of nanometer thick gallium arsenide (GaAs) can be a proper candidate due to its high carrier concentration in low energy band gap. To obtain highly doped GaAs in molecular beam epitaxy, the temperatures of Si Knudsen cell (K-cell) for n-type GaAs and Be K-cell for p-type GaAs were controlled during GaAs epitaxial growth, and the growth rate is set to 1.75 A/s. As a result, the doping concentration of p-type and n-type GaAs increased up to $4.7{\times}10^{19}cm^{-3}$ and $6.2{\times}10^{18}cm^{-3}$, respectively. However, the obtained n-type doping concentration is not sufficient to form a properly operating tunnel diode which requires a doping concentration close to $1.0{\times}10^{19}cm^{-3}$ [2]. To enhance the n-type doping concentration, n-doped GaAs samples were grown with a lower growth rate ranging from 0.318 to 1.123 A/s at a Si K-cell temperature of $1,180^{\circ}C$. As shown in Fig. 1, the n-type doping concentration was increased to $7.7{\times}10^{18}cm^{-3}$ when the growth rate was decreased to 0.318 A/s. The p-type doping concentration also increased to $4.1{\times}10^{19}cm^{-3}$ with the decrease of growth rate to 0.318 A/s. Additionally, bulk resistance was also decreased in both the grown samples. However, a transmission line measurement performed on the n-type GaAs sample grown at the rate of 0.318 A/s showed an increased specific contact resistance of $6.62{\times}10^{-4}{\Omega}{\cdot}cm^{-2}$. This high value of contact resistance is not suitable for forming contacts and interfaces. The increased resistance is attributed to the excessively incorporated dopant during low growth rate. Further studies need to be carried out to evaluate the effect of excess dopants on the operation of tunnel diode.

• 한국융합학회논문지
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• 제8권8호
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• pp.9-15
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• 2017

반도체 집적 기술의 발전으로 중앙처리장치 및 저장장치가 소형화되고 성능이 빠르게 발전되면서 고성능 컴퓨팅(High Performance Computing) 분야에서 인터커넥션 네트워크가 전체 시스템의 성능을 결정하는데 더욱 중요한 요소가 되고 있다. 본 논문에서는 고성능컴퓨팅 분야에서 사용되는 인터커넥션 네트워크 기술 동향을 분석하였다. 2017년 6월 기준 슈퍼컴퓨터 Top 500에서 가장 많이 사용하고 있는 인터커텍트는 인피니밴드이다. 최근 이더넷은 40/100Gbps 기가비트 이더넷 기술의 등장으로 인피니밴드 다음으로 높은 점유율을 보이고 있다. 지연(latency) 성능이 인피니밴드에 비해 떨어지는 기가비트 이더넷은 비용 대비 효율을 중시하는 중형급 데이터 센터에서 선호하고 있다. 또한 고성능을 요구하는 최상위 HPC 시스템들은 기존의 이더넷, 인피니밴드 기술에서 벗어나, 자체적인 인터커넥트 네트워크를 도입하여 시스템의 성능을 극대화 하는 노력을 하고 있다. 향후 고성능 인터커넥트 분야는 전기 신호기반 데이터 통신에서 한 단계 도약하여, 빛으로 데이터를 주고받는 실리콘 반도체 기반 광송수신 기술이 활용될 것으로 예상된다.

• Korean Chemical Engineering Research
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• 제45권5호
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• pp.466-472
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• 2007

웨이퍼 레벨(WL) 3차원(3D) 집적을 구현하기 위해 저유전체 고분자를 본딩 접착제로 이용한 웨이퍼 본딩과, 적층된 웨이퍼간 전기배선 형성을 위해 구리 다마신(damascene) 공정을 사용하는 방법을 소개한다. 이러한 방법을 이용하여 웨이퍼 레벨 3차원 칩의 특성 평가를 위해 적층된 웨이퍼간 3차원 비아(via) 고리 구조를 제작하고, 그 구조의 기계적, 전기적 특성을 연속적으로 연결된 서로 다른 크기의 비아를 통해 평가하였다. 또한, 웨이퍼간 적층을 위해 필수적인 저유전체 고분자 수지를 이용한 웨이퍼 본딩 공정의 다음과 같은 특성 평가를 수행하였다. (1) 광학 검사에 의한 본딩된 영역의 정도 평가, (2) 면도날(razor blade) 시험에 의한 본딩된 웨이퍼들의 정성적인 본딩 결합력 평가, (3) 4-점 굽힘시험(four point bending test)에 의한 본딩된 웨이퍼들의 정량적인 본딩 결합력 평가. 본 연구를 위해 4가지의 서로 다른 저유전체 고분자인 benzocyclobutene(BCB), Flare, methylsilsesquioxane(MSSQ) 그리고 parylene-N을 선정하여 웨이퍼 본딩용 수지에 대한 적합성을 검토하였고, 상기 평가 과정을 거쳐 BCB와 Flare를 1차적인 본딩용 수지로 선정하였다. 한편 BCB와 Flare를 비교해 본 결과, Flare를 이용하여 본딩된 웨이퍼들이 BCB를 이용하여 본딩된 웨이퍼보다 더 높은 본딩 결합력을 보여주지만, BCB를 이용해 본딩된 웨이퍼들은 여전히 칩 back-end-of-the-line (BEOL) 공정조건에 부합되는 본딩 결합력을 가지는 동시에 동공이 거의 없는 100%에 가까운 본딩 영역을 재현성있게 보여주기 때문에 본 연구에서는 BCB가 본딩용 수지로 더 적합하다고 판단하였다.