• Korean Journal of Remote Sensing
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• v.8 no.1
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• pp.59-69
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• 1992

The IMAPRO sotfware package was mainly focused to provide an algorithm which is capable of displaying various color composite images on IBM PC, VGA(Video Graphic Array) card with no special hardware. It displays the false color images using a low-cost eight-bit place refresh buffer. This produces similar quality to the one obtained from image board with three eight-bit plane. Also, it provides user friendly menu driven method for the user who are not familier with technical knowladge of image processing. It may prove useful for universities, institute and private company where expensive hardware is not available.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.25-26
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• 2009

아두이노 보드는 Atmel 8 비트 RISC 마이크로프로세서를 이용해서 제작된 임베디드 보드이다. 마이크로프로세서 내부에 프로그램을 쓸 수 있다는 기능과 하드웨어 설계도가 오픈소스로 제작된다는 점, 일반 사용자들을 위해서 제공되는 쉬운 개발 언어 및 개발 환경을 제공한다. 본 논문에서는 아두이노 보드 위에서 동작하는 임베디드 소프트웨어에 대해 테스트하는 방법과 앞으로의 테스트 방법에 대한 개발방향에 대하여 논한다.

• Aerospace Engineering and Technology
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• v.13 no.2
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• pp.7-17
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• 2014

This technical paper deals with development of on-board orbit generation algorithm for GEO Satellite. This paper presents the research analysis results performed in order to improve the accuracy of the existing algorithm used for generating real-time orbit information for GEO satellite. The error impact on orbit accuracy due to the orbit error sources were analyzed with the algorithm suggested by this research. As a result of the analyses, it is found that the initial orbit should be determined with an accuracy of less than 50 m and the reference position angle error for the ground station and the satellite should be maintained within ${\pm}0.0025deg$ in order to meet the orbit accuracy specification. The development of on-board flight software based on the new algorithm was accomplished and the performance verification is ongoing by using a software based performance verification tool.

• Journal of Software Assessment and Valuation
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• v.17 no.2
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• pp.161-172
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• 2021

Neuromorphic architecture is drawing attention as a next-generation computing that supports artificial intelligence technology with low energy. However, FPGA embedded boards based on Neuromorphic architecturehave limited resources due to size and power. In this paper, we compared and evaluated the image reduction method using the interpolation method that rescales the size without considering the feature points and the DCT (Discrete Cosine Transform) method that preserves the feature points as much as possible based on energy. The scaled images were compared and analyzed for accuracy through CNN (Convolutional Neural Networks) in a PC environment and in the Nengo framework of an FPGA embedded board.. As a result of the experiment, DCT based classification showed about 1.9% higher performance than that of interpolation representation in both CNN and FPGA nengo environments. Based on the experimental results, when the DCT method is used in a limited resource environment such as an embedded board, a lot of resources are allocated to the expression of neurons used for classification, and the recognition rate is expected to increase.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.280-288
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• 2009

In this paper, we developed new time information recording module of VSI (VLBI Standard Interface) format by analyzing the Mark5B recorder control and operation software with 1Gbps speed, which is able to record the weak signal of space radio source, through the Korean VLBI Network (KVN). The control and operation software of high-speed recorder consists of 2 kinds of software, which is that it can operate RAID control board by controlling large capacity HDD drive and the network control and operation. Especially, core software in high-speed recorder is able to output the results after performing and analyzing the input command. Through the analysis of control and operation software, new time information recording module, which is needed to process the observed data for correlation, is developed. New developed time information recording module can record the time information together after checking the interrupt of 1PPS(Pulse Per Second) input signal when the observed data will be recorded. To verify the normal operation of the developed time information recording module, we performed the real observation test and confirmed the effectiveness of developed software through analyzing the recorded observation data.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• The Journal of the Convergence on Culture Technology
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• v.4 no.3
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• pp.293-298
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• 2018

In the fourth industrial revolution era triggered by the popularization of smart phones, Human daily life and all industrial sites are becoming software and intelligent. With the universal software education for all students nationwide from 2018, Demand is surging, and hardware is interlocked using software technology and Arduino. However, expensive control boards and dozens of different electronic components have to be prepared separately and problems are occurring. In addition, if the same training is repeated, Significantly many parts are lost or destroyed. Being prepared to start a new class is also becoming a very serious problem. In this study, we implement VR technology based on virtualization technology of Arduino board and various electronic parts. In addition, 3D graphics realistic Arduino kit and various electronic components are provided in API form. In this paper, we propose a method of interworking software and virtual hardware on virtualization base.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.10
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• pp.903-910
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• 2000

In this paper, we describe a slave chip based on the Profibus-DP protocol and a system board to verify the developed slave chip. The Profibus-DP protocol is designed using VHDL and implemented on FPGA. The system board adopting the developed FPGA is designed FPGA is designed in which the firmware is implemented on Intel 8051 by using C language. Among the Profibus-DP protocols, low level layers from the physical layer to the data link layer is implemented in the form of hardware that we are able to greatly reduce the CPU load in processing protocols, and then higher layers could be processed by software. These technologies result in an IP to make terminal devices in the distributed control systems. Therefore, many digital logics as well as communication logics can be implemented onto SOC(System On a Chip) and it could be applied to various fieldbus-related areas.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.140.4-140
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• 2001

This paper presents the duplex controller operated as master slave for Self Excited Static Type excitation system and the results of operation for duplex digital excitation system. Software is made up duplex multi-tasking control algorithm which is based on VxWorks(real-time OS), preprocessing algorithm for input-output signal, BSP & Device Driver for interfacing hardware and software, and OIS(Operator Interface Station) program, HMI S/W. Master controller and slave controller intercommunicate dominant data to minimize bump when controller switchover from master to slave occurs. Communication between master controller and slave controller is duplicated and communication between OIS and controller is duplicated. Hardware is made up VMEBUS based controller which is designed with PPC & I/O board ...

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.417-422
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• 1990

For the robot manipulator in performing precision task, it is indispensable that the robot utilize the various sensors for intelligence. This paper presents the development and implementation of an integrated control system for the control of robotic manipulator, a feeder, a conveyor belt system, force/torque sensor system, and a photo sensor system. Micro controller board was constructed for hierarchical control of the system. To set up the program interactively, a user can make use of the software which includes the full-down menu and a dialog box. The user can make progress the program quickly and easily by a mouse. The related software was written in C and assembly languages.