• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.37-40
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• 1999

For the first time, charge trapping nonvolatile semiconductor memories with the deoxidized oxynitride gate dielectric is proposed and demonstrated. Gate dielectric wit thickness of less than 1 nm have been grown by postnitridation of pregrown thermal silicon oxides in NO ambient and then reoxidation. The nitrogen distribution and chemical state due to NO anneal/reoxidation were investigated by M-SIMS, TOF-SIMS, AES depth profiles. When the NO anneal oxynitride film was reoxidized on the nitride film, the nitrogen at initial oxide interface not only moved toward initial oxide interface, but also diffused through the newly formed tunnel oxide by exchange for oxygen. The results of reoxidized oxynitride(ONO) film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/N-rich SiON interface/Si-rich SiON(nitrogen diffused tunnel oxide)/Si substrate. In addition, the SiON and the S1$_2$NO Phase is distributed mainly near the tunnel oxide, and SiN phase is distributed mainly at tunnel oxide/Si substrate interface.

• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.75-78
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• 2004

$Bi_{3.25}Eu_{0.75}Ti_3O_{12}$ (BET) thin films were deposited on the $LaNiO_3$ (LNO (100))/Si and Pt/Ti/$SiO_2$/Si substrates by the metal-organic decomposition method. Structural and dielectric properties of BLT thin films for the applications in nonvolatile ferroelectric random access memories were investigated. Both the structure and morphology of the films were analyzed by x-ray diffraction (XRD) and atomic force microscope (AFM). Even at low temperatures $650^{\circ}C$, the BET thinfilms were successfully deposited on LNO bottom electrode and exhibited (001) and (117) orientation. Compared with the Pt electrode films, the BET thin films on the LNO electrode annealed at $650^{\circ}C$ showed better dielectric constantsand remanent polarization. The BET thin films on the LNO electrode for the annealing temperature of $650^{\circ}C$, the remanent polarization Pr and coercive field were $45.6\;C/cm^2$ and 171 kV/cm, respectively.

• Journal of the Korean institute of surface engineering
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• v.51 no.6
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• pp.387-392
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• 2018

Nanopatterning is one of the essential nanotechnologies to fabricate electronic and energy nanodevices. Therefore, many research group members made a lot of efforts to develop simple and useful nanopatterning methods to obtain highly ordered nanostructures with functionality. In this study, in order to achieve pattern formation of three-dimensional (3D) hierarchical nanostructures, we introduce a simple and useful patterning method (nano-transfer printing (n-TP) process) consisting of various linewidths for diverse materials. Pt and $WO_3$ hybrid line structures were successfully stacked on a flexible polyimide substrate as a multi-layered hybrid 3D pattern of Pt/WO3/Pt with line-widths of $1{\mu}m$, $1{\mu}m$ and 250 nm, respectively. This simple approach suggests how to fabricate multiscale hybrid nanostructures composed of multiple materials. In addition, functional hybrid nanostructures can be expected to be applicable to various next-generation electronic devices, such as nonvolatile memories and energy harvesters.

• Journal of Information Display
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• v.10 no.4
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• pp.149-157
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• 2009

Reported herein is the architecture for a nonvolatile n-type memory paper field-effect transistor. The device was built via the hybrid integration of natural cellulose fibers (pine and eucalyptus fibers embedded in resin with ionic additives), which act simultaneously as substrate and gate dielectric, using passive and active semiconductors, respectively, as well as amorphous indium zinc and gallium indium zinc oxides for the gate electrode and channel layer, respectively. This was complemented by the use of continuous patterned metal layers as source/drain electrodes.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.4
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• pp.213-225
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• 2007

Flash memory is widely used as a storage device for potable equipments such as digital cameras, MP3 players and cellular phones because of its characteristics such as its large volume and nonvolatile feature, low power consumption, and good performance. However, a block in flash memories should be erased to write because of its hardware characteristic which is called as erase-before-write architecture. The erase operation is much slower than read or write operations. FTL is used to overcome this problem. We compared the performance of the existing FTL algorithms on Windows-based OS. We have developed a tool called FTL APAT in order to gather I/O patterns of the disk and analyze the performance of the FTL algorithms. It is the log buffer scheme with full associative sector translation(FAST) that the performance is best.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.4
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• pp.77-81
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• 2020

Resistive RAM (ReRAM) is a strong candidate for the next-generation nonvolatile memories which use the resistive switching characteristic of transition metal oxides. The resistive switching behaviors originate from the redistribution of oxygen vacancies inside of the oxide film by applied programming voltage. Therefore, controlling the oxygen vacancy inside transition metal oxide film is most important to obtain and control the resistive switching characteristic. In this study, we introduced an applying electric field into photochemical metal-organic deposition (PMOD) process to control the oxidation state of metal oxide thin film during the photochemical reaction by UV exposure. As a result, the surface oxidation state of FeOx film could be successfully controlled by the electric field-assisted PMOD (EFAPMOD), and the controlled oxidation states were confirmed by x-ray photoelectron spectroscopy (XPS) I-V characteristic. And the resistive switching characteristics with the oxidation-state of the surface region could be controlled effectively by adjusting an electric field during EFAPMOD process.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.6
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• pp.304-310
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• 2002

Novel charge trap type memory devices with reoxidized oxynitride gate dielectrics made by NO annealing and reoxidation process of initial oxide on substrate have been fabricated using 0.35 $\mu \textrm{m}$ retrograde twin well CMOS process. The feasibility for application as NVSM memory device and characteristics of traps have been investigated. For the fabrication of gate dielectric, initial oxide layer was grown by wet oxidation at $800^{\circ}C$ and it was reoxidized by wet oxidation at $800^{\circ}C$ after NO annealing to form the nitride layer for charge trap region for 30 minutes at $850^{\circ}C$. The programming conditions are possible in 11 V, 500 $\mu \textrm{s}$ for program and -13 V, 1ms for erase operation. The maximum memory window is 2.28 V. The retention is over 20 years in program state and about 28 hours in erase state, and the endurance is over $3 \times 10^3$P/E cycles. The lateral distributions of interface trap density and memory trap density have been determined by the single junction charge pumping technique. The maximum interface trap density and memory trap density are $4.5 \times 10^{10} \textrm{cm}^2$ and $3.7\times 10^{18}/\textrm{cm}^3$ respectively. After $10^3$ P/E cycles, interlace trap density increases to $2.3\times 10^{12} \textrm{cm}^2$ but memory charges decreases.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.173-173
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• 2010

$Bi_4Ti_3O_{12}$ ($B_4T_3$) is a unique ferroelectric material that has a relatively high dielectric constant, high Curie temperature, high breakdown strength, and large spontaneous polarization. As a result this material has been widely studied for many applications, including nonvolatile ferroelectric random memories, microelectronic mechanical systems, and nonlinear-optical devices. Several reports have appeared on the use of Mn dopants to improve the electrical properties of $B_4T_3$ thin films. Mn ions have frequently been used for this purpose in thin films and multilayer capacitors in situations where intrinsic oxygen vacancies are the major defects. However, no systematic study of the optical properties of $B_4T_3$ films has appeared to date. Here, we report optical data for these films, determined by spectroscopic ellipsometry (SE). We also report the effects of thermal annealing and Mn doping on the optical properties. The SE data were analyzed using a multilayer model that is consistent with the original sample structure, specifically surface roughness/$B_4T_3$ film/Pt/Ti/$SiO_2$/c-Si). The data are well described by the Tauc-Lorentz dispersion function, which can therefore be used to model the optical properties of these materials. Parameters for reconstructing the dielectric functions of these films are also reported. The SE data show that thermal annealing crystallizes $B_4T_3$ films, as confirmed by the appearance of $B_4T_3$ peaks in X-ray diffraction patterns. The bandgap of $B_4T_3$ red-shifts with increasing Mn concentration. We interpret this as evidence of the existence deep levels generated by the Mn transition-metal d states. These results will be useful in a number of contexts, including more detailed studies of the optical properties of these materials for engineering high-speed devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.319-322
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• 2003

To match the charge induced by the insulators $CeO_2$ with the remanent polarization of ferro electric SBT thin films, areas of Pt/SBT/Pt (MFM) and those of $Pt/CeO_2/Si$ (MIS) capacitors were ind ependently designed. The area $S_M$ of MIS capacitors to the area $S_F$ of MFM capacitors were varied from 1 to 10, 15, and 20. Top electrode Pt and SBT layers were etched with for various area ratios of $S_M\;/\;S_F$. Bottom electrode Pt and $CeO_2$ layers were respectively deposited by do and rf sputtering in-situ process. SBT thin film were prepared by the metal orgnic decomposition (MOD) technique. $Pt(100nm)/SBT(350nm)/Pt(300nm)/CeO_2(40nm)/p-Si$ (MFMIS) gate structures have been fabricated with the various $S_M\;/\;S_F$ ratios using inductively coupled plasma reactive ion etching (ICP-RIE). The leakage current density of MFMIS gate structures were improved to $6.32{\times}10^{-7}\;A/cm^2$ at the applied gate voltage of 10 V. It is shown that in the memory window increase with the area ratio $S_M\;/\;S_F$ of the MFMIS structures and a larger memory window of 3 V can be obtained for a voltage sweep of ${\pm}9\;V$ for MFMIS structures with an area ratio $S_M\;/\;S_F\;=\;6$ than that of 0.9 V of MFS at the same applied voltage. The maximum memory windows of MFMIS structures were 2.28 V, 3.35 V, and 3.7 V with the are a ratios 1, 2, and 6 at the applied gate voltage of 11 V, respectively. It is concluded that ferroelectric gate capacitors of MFMIS are good candidates for nondestructive readout-nonvolatile memories.