• ETRI Journal
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• v.33 no.1
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• pp.27-31
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• 2011

This paper addresses estimating the frequency of a cisoid in the presence of white Gaussian noise, which has numerous applications in communications, radar, sonar, and instrumentation and measurement. Due to the nonlinear nature of the frequency estimation problem, there is threshold effect, that is, large error estimates or outliers will occur at sufficiently low signal-to-noise ratio (SNR) conditions. Utilizing the ideas of averaging to increase SNR and weighted linear prediction, an optimal frequency estimator with smaller threshold SNR is developed. Computer simulations are included to compare its mean square error performance with that of the maximum likelihood (ML) estimator, improved weighted phase averager, generalized weighted linear predictor, and single weighted sample correlator as well as Cramer-Rao lower bound. In particular, with smaller computational requirement, the proposed estimator can achieve the same threshold and estimation performance of the ML method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1288-1298
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• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.