• 한국전기전자재료학회논문지
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• 제17권11호
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• pp.1149-1155
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• 2004

In this paper, novel methods for improvement of thermal stability of Ni-germano Silicide were proposed for nano CMOS applications. It was shown that there happened agglomeration and abnormal oxidation in case of Ni-germano Silicide using Ni only structure. Therefore, 4 kinds of tri-layer structure, such as, Ti/Ni/TiN, Ni/Ti/TiN, Co/Ni/TiN and Ni/Co/TiN were proposed utilizing Co and Ti interlayer to improve thermal stability of Ni-germano Silicide. Ti/Ni/TiN structure showed the best improvement of thermal stability and suppression of abnormal oxidation although all kinds of structures showed improvement of sheet resistance. That is, Ti/Ni/TiN structure showed only 11 ohm/sq. in spite of 600 $^{\circ}C$, 30 min post silicidation annealing while Ni-only structure show 42 ohm/sq. Therefore, Ti/Ni/TiN structure is highly promising for nano-scale CMOS technology.

• 대한전자공학회논문지SD
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• 제43권12호
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• pp.33-39
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• 2006

나노 스케일 벌크 MOSFET의 RF 비선형 특성을 넓은 bias영역에 걸쳐 정확히 예측하기 위하여 내된 비선형 요소들을 가진 엠피리컬 비선형 모델이 새롭게 구축되었다. 먼저, 나노 스케일 벌크 MOSFET에 적합한 파라미터 추출방법을 사용하여 측정된 S-파라미터로부터 bias 종속 내부 파라미터 곡선을 추출하였다. 그 후에 비선형 캐패시턴스 및 전류원 방정식들은 추출된 bias 종속 곡선들과 3차원 fitting함으로서 엠피리컬하게 구하여졌다. 이와 같이 모델된 S-파라미터는 60nm MOSFET의 측정치와 20GHz 까지 아주 잘 일치하였으며, 이는 엠피리컬 나노 MOSFET 모델의 정확도를 증명한다

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.139-141
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• 2006

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nano-electronic devices which will inherit the throne of CMOS which is the domineering implementation technology of large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors. After the gate and interconnect structures of the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit QCA adder. The digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• 대한전자공학회논문지SD
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• 제41권11호
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• pp.1-6
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• 2004

RFIC를 위한 Nanoscale MOSFET에서의 유효 게이트 저항을 직접 추출법으로 추출하여 다양한 게이트 길이에 대해 분석하였다. 추출된 유효 게이트 저항은 비교적 정확하면서 간소화된 모델을 통한 측정결과와 비교하여 10GHz 대역까지 잘 일치함을 확인하였다. 같은 공정기술로 제작된 소자들 중에서 reverse short channel 효과가 생기지 않는 긴 채널 MOSFET 소자의 경우에 일반적인 유효 게이트 저항에서와는 다른 인가전압 및 주파수 종속성을 가짐을 확인하였다. 특히, 문턱전압을 전후하여 주파수에 따라 상이한 결과를 나타내고 있으며, 게이트 인가전압이 문턱전압에 가까울 때 비이상적으로 큰 유효 게이트 저항값을 나타내었다. 이러한 특성은 직접추출법을 사용하는 RF MOSFET 모델링에 있어서 참고해야 할 중요한 특성이 될 것이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.53-58
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• 2012

A new on-wafer de-embedding method using thru, short and open patterns sequentially is proposed to eliminate the errors of conventional methods. This "thru-short-open" method is based on the removal of the coupling admittance between input and output interconnect dangling legs. The increase of the de-embedding effect of the lossy coupling capacitance on the cutoff frequency in MOSFETs is observed as the gate length is scaled down to 45 nm. This method will be very useful for accurate RF measurements of nano-scale MOSFETs.

• Transactions on Electrical and Electronic Materials
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• 제12권5호
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• pp.175-188
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• 2011

As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.

• 대한전자공학회논문지SD
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• 제42권12호
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• pp.1-8
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• 2005

본 연구에서는 측정된 S-파라미터로부터 추출된 Nano-scale MOSFET 등가회로 파라미터의 scaling 방정식을 사용하여 차단주파수의 게이트 길이 종속성을 모델화하였다. 모델된 차단주파수는 게이트 길이가 줄어듬에 따라서 크게 증가하다가, 점점 증가율이 크게 감소하는 경향을 보였다. 이는 게이트 길이가 감소함에 따라 내부전달시간은 크게 줄어들지만, 외부 기생 충전시간은 상대적으로 조금씩 감소하기 때문이다. 이와 같은 새로운 게이트길이 종속 모델은 Nano-scale MOSFET의 RF성능을 최적화시키는 데 큰 도움이 될 것이다.

• 전기전자학회논문지
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• 제18권2호
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• pp.228-233
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• 2014

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

• 한국전기전자재료학회논문지
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• 제20권1호
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• pp.1-7
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• 2007

In this paper, two kinds of initial oxidation methods i.e., SLTO(Slow Low Temperature Oxidation: $700^{\circ}C$) and RTO(Rapid Thermal Oxidation: $850^{\circ}C$) are applied prior to the plasma nitridation for ultra thin oxide of RPNO (Remote Plasma Nitrided Oxide). It is observed that SLTO has superior characteristics to RTO such as lower SS(Sub-threshold Slope) and improved Ion-Ioff characteristics. Low frequency noise characteristics of SLTO also showed better than RTO both in linear and saturation regime. It is shown that flicker noise is dominated by carrier number fluctuation in the channel region. Therefore, SLTO is promising for nano-scale CMOS technology with ultra thin gate oxide.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.327-330
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• 2004

It is shown that the hot carrier degradation due to enhanced hot holes trapping dominates PMOSFETs lifetime both in thin and thick devices. Moreover, it is found that in 0.13 ${\mu}m$ CMOSFET the PMOS lifetime under CHC (Channel Hot Carrier) stress is lower than the NMOSFET lifetime under DAHC (Drain Avalanche Hot Carrier) stress. Therefore. the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method and highly necessary to enhance overall device lifetime or circuit lifetime in upcoming nano-scale CMOS technology.