• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• Journal of the Korean Ceramic Society
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• v.37 no.5
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• pp.432-437
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• 2000

Thermoelectric properties of p-type SiGe alloys prepared by a RF inductive furnace were investigated. Non-doped Si80Ge20 alloys were fabricated by control of the quantity of volatile Ge. The carrier of p-type SiGe alloy was controlled by B-doping. B doped p-type SiGe alloys were synthesized by melting the mixture of Ge and Si containing B. The effects of sintering/annealing conditions and compaction pressure on thermoelectric properties (electrical conductivity and Seebeck coefficient) were investigated. For nondoped SiGe alloys, electrical conductivity increased with increasing temperatures and Seebeck coefficient was measured negative showing a typical n-type semiconductivity. On the other hand, B-doped SiGe alloys exhibited positive Seebeck coefficient and their electrical conductivity decreased with increasing temperatures. Thermoelectric properties were more sensitive to compaction pressure than annealing time. The highest power factor obtained in this work was 8.89${\times}$10-6J/cm$.$K2$.$s for 1 at% B-doped SiGe alloy.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.289-289
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• 2013

While there are plenty of studies on synthesizing semiconducting germanium nanowires (Ge NWs) by vapor-liquid-solid (VLS) process, it is difficult to inject dopants into them with uniform dopants distribution due to vapor-solid (VS) deposition. In particular, as precursors and dopants such as germane ($GeH_4$), phosphine ($PH_3$) or diborane ($B_2H_6$) incorporate through sidewall of nanowire, it is hard to obtain the structural and electrical uniformity of Ge NWs. Moreover, the drastic tapered structure of Ge NWs is observed when it is synthesized at high temperature over $400^{\circ}C$ because of excessive VS deposition. In 2006, Emanuel Tutuc et al. demonstrated Ge NW pn junction using p-type shell as depleted layer. However, it could not be prevented from undesirable VS deposition and it still kept the tapered structures of Ge NWs as a result. Herein, we adopt $C_2H_2$ gas in order to passivate Ge NWs with carbon sheath, which makes the entire Ge NWs uniform at even higher temperature over $450^{\circ}C$. We can also synthesize non-tapered and uniformly doped Ge NWs, restricting incorporation of excess germanium on the surface. The Ge NWs with carbon sheath are grown via VLS process on a $Si/SiO_2$ substrate coated 2 nm Au film. Thin Au film is thermally evaporated on a $Si/SiO_2$ substrate. The NW is grown flowing $GeH_4$, HCl, $C_2H_2$ and PH3 for n-type, $B_2H_6$ for p-type at a total pressure of 15 Torr and temperatures of $480{\sim}500^{\circ}C$. Scanning electron microscopy (SEM) reveals clear surface of the Ge NWs synthesized at $500^{\circ}C$. Raman spectroscopy peaked at about ~300 $cm^{-1}$ indicates it is comprised of single crystalline germanium in the core of Ge NWs and it is proved to be covered by thin amorphous carbon by two peaks of 1330 $cm^{-1}$ (D-band) and 1590 $cm^{-1}$ (G-band). Furthermore, the electrical performances of Ge NWs doped with boron and phosphorus are measured by field effect transistor (FET) and they shows typical curves of p-type and n-type FET. It is expected to have general potentials for development of logic devices and solar cells using p-type and n-type Ge NWs with carbon sheath.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.9
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• pp.770-775
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• 2002

We present the band lineups of G $e_{1-}$x S $n_{x}$ G $e_{1-}$y S $n_{y(001)}$ heterostructures for the new devices. The energy gap of the bulk G $e_{1-}$x S $n_{x}$ alloy is calculated by taking into account the Vegard's law. The change of the energy gap due to the strain is understood in terms of the deformation Potential theory The valence band offset is obtained from the average bond energy model, where the changes of the band offset due to alloy compositions and strain are included. It is found that Ge/G $e_{1-}$y S $n_{y(001)}$ heterostructure has a staggered lineup type for 0$\leq$0.06 and a straddling one for 0.06$\leq$0.26. Meanwhile, Ge/G $e_{l-y}$ S $n_{y(001)}$ heterostructure has a staggered lineup type for 0$\leq$0.19 and a broken-gap one for 0.19$\leq$0.26. As a result, the various type of the G $e_{1-}$x S $n_{x}$ G $e_{1-}$y S $n_{y(001)}$ heterostructure can be applied for the useful device.evice.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.10
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• pp.852-858
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• 2007

The dependence of substrate on the Ag photodoping phenomenon into amonhous $({\alpha}-)$ GeSe thin film has been investigated using holographic method. A 442 nm HeCd laser was utilized as a light source for the holographic exposure and a 632.8 nm HeNe laser to measure the variation of diffraction efficiency $(\eta)$ in real time. The films (Ag and ${\alpha}-GeSe$) were thermally deposited on the substrates, i.e. p-type Si(100), n-type Si(100) and slide glass. The sample structures prepared were two types: type I (Ag/${\alpha}$-SeGe/substrate) and type II (${\alpha}$-SeGe/Ag/substrate). The $\eta$ kinetics comprised to be three steps in which $\eta$ initially increases, is saturated to be maximized $(\eta_M)$, and then decreases relatively gradually. For the same substrate, the $\eta_M$ values of the type II were higher than those of type I. In addition, the type II exhibited the highest $\eta_M$ for p-type Si substrate, while that in type I was observed for n-type Si substrate. These tendency is explained by the diffusion of minority carrier in the films and the change of magnitude and direction in internal fields generated at the film interfaces. Atomic-force-microscope (AFM) was used to observe relief-type grating patterns.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.75-76
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• 2006

New PM route via bulk mechanical alloying is developed to fabricate the solid solution semi-conductive materials with $Mg_2Si_{1-x}Ge_x$ and $Mg_2Si_{1-y}Sn_y$ for 0 < x, y < 1 and to investigate their thermoelectric materials. Since $Mg_2Si$ is n-type and both $Mg_2Ge$ and $Mg_2Sn$ are p-type, pn-transition takes place at the specified range of germanium content, x, and tin content, y. Through optimization of chemical composition, solid-solution type thermoelectric semi-conductive materials are designed both for n-and p-type materials.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.847-853
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• 2016

Applications of Si have been increasingly exploited and extended to More-Moore, More-than-Moore, and beyond-CMOS approaches. Ge is regarded as one of the supplements for Si owing to its higher carrier mobilities and peculiar band structure, facilitating both advanced and optical applications. As an emerging metal-oxide device, the junctionless field-effect transistor (JLFET) has drawn considerable attention because of its simple process, less performance fluctuation, and stronger immunity against short-channel effects due to the absence of anisotype junctions. In this study, we investigated lateral field scalability, which is equivalent to channel-length scaling, in Si and Ge JLFETs. Through this, we can determine the usability of Si CMOS and hypothesize its replacement by Ge. For simulations with high accuracy, we performed rigorous modeling for ${\mu}_n$ and ${\mu}_p$ of Ge, which has seldom been reported. Although Ge has much higher ${\mu}_n$ and ${\mu}_p$ than Si, its saturation velocity ($v_{sat}$) is a more determining factor for maximum $I_{on}$. Thus, there is still room for pushing More-Moore technology because Si and Ge have a slight difference in $v_{sat}$. We compared both p- and n-type JLFETs in terms of $I_{on}$, $I_{off}$, $I_{on}/I_{off}$, and swing with the same channel doping and channel length/thickness. $I_{on}/I_{off}$ is inherently low for Ge but is invariant with $V_{DS}$. It is estimated that More-Moore approach can be further driven if Si is mounted on a JLFET until Ge has a strong possibility to replace Si for both p- and n-type devices for ultra-low-power applications.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.7
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• pp.354-358
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• 2006

In this paper, we investigated the selective etching rate of amorphous As-Ge-Se-S thin film due to the photoexpansion effect and fabricated the 2-dimensional embossing type diffraction grating hologram. We measured the thickness change with the etching time among NaOH solution after forming 1-dimension diffraction grating. As a results, we found that the selective etching rate were $2.5\AA/s,\;3.3\AA/s,\;3.9\AA/s$ where NaOH solution concentration were 0.26N, 0.33N, 0.36N, respectively. Also after the formation of 2-dimensional diffraction grating by the $90^{\circ}$ degree of circulation on the formed 1-dimensional diffraction grating, we etched selectively during 60sec, among 0.26N NaOH solution and obtained 2-dimensional embossing diffraction grating. As the results of AFM (Atomic Force Microscopy), we confirmed the formation of distinct embossing type 2-dimensional diffraction grating hologram, successfully.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.356-356
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• 2013

Monolithic 3D-IC는 현대 집적회로에서 interconnect로 인해 발생되는 여러 문제들을 해결하기 위해 새롭게 제시되고 있는 기술적 개념으로 구현 시 하위 소자 및 interconnet들에 영향을 주지 않는 저온공정이 필수적이다. 특히 germanium (Ge)은 낮은 녹는점 및 높은 캐리어 이동도 덕분에 3D-IC 구현 시 상위 소자의 channel 물질에 적합한 것으로 알려져 있다. 최근 이러한 Ge을 결정화하기 위해 solid phase crystallization (SPC), metal induced crystallization (MIC), laser annealing과 같은 결정화 방법들이 보고되고 있다. 현재까지 SPC 방법에 의해 얻어진 poly-Ge의 도핑농도 및 이동도와 같은 전기적 특성에 대한 분석은 수행된 바 있으나 3D-IC 공정에 적용이 가능한 MIC 기술을 통해 얻어진 poly Ge 필름에 대한 전기적 특성분석은 부족한 상황이다. 본 연구는 SPC 뿐만 아니라 MIC 방법을 통해 ${\alpha}$-Ge를 결정화시키고 얻어진 poly-Ge 필름의 전기적 특성을 XRD 및 hall effect measurement를 통해 분석하였다. 특히 일반적으로 Ge 내에서 p-type dopant로 동작을 하는 defect과 n-type dopant인 phosphorus 관계를 고려하여 여러 온도에서 SPC 및 MIC에 의해 얻어진 phosphorus doped poly-Ge 필름들의 전기적 특성을 분석하였다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.675-678
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• 2003

본 논문에서는 N-type 기판에서 Nickel-Silicide를 적용하였을 경우에 나타나는 문제점과 PAI (Pre-amorphization Implant)의 효과에 대하여 알아보았다. N-type 기판에 RTP (Rapid Thermal Process)를 통하여 Nickel-Silicide 를 형성하게 되는데, 여기까지는 안정한 Nickel mono-Silicide (NiSi)가 형성됨을 확인하였다. 하지만 후속 열처리 공정 후 심한 응집 현상 (Agglomeration)과 이상 산화 현상 (Abnormal Oxidation Phenomenon), Silicide Island 등 열안정성 (Thermal Stability) 측면에서 여러 가지 많은 문제점들이 나타났다. 이 후속 열처리의 열안정성 취약점들을 극복하는 방안으로 Ge 및 N₂ PAI를 적용하였다. PAI를 적용하였을 경우에는 그렇지 않은 경우에 비하여 고온 열처리 후에도 면저항이 비교적 잘 유지되었으며, 두께가 얇고 안정한 Nickel-Silicide 특성을 확보할 수 있었다. 특히 Ge PAI 에 비하여 N₂ PAI 의 경우가 보다 특성 개선 효과가 크게 나타났다.