• Journal of Korea Multimedia Society
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• v.9 no.1
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• pp.119-126
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• 2006

The task scheduling in multiprocessor system is one of the key elements in the effective utilization of multiprocessor systems. The optimal assignment of tasks to multiprocessor is, in almost practical cases, an NP-hard problem. Consequently algorithms based on various modern heuristics have been proposed for practical reason. This paper proposes a new task scheduling algorithm using Genetic Algorithm which combines simulated annealing (GA+SA) in multiprocessor environment. In solution algorithms, the Genetic Algorithm (GA) and the simulated annealing (SA) are cooperatively used. In this method, the convergence of GA is improved by introducing the probability of SA as the criterion for acceptance of new trial solution. The objective of proposed scheduling algorithm is to minimize makespan. The effectiveness of the proposed algorithm is shown through simulation studies. In simulation studies, the result of proposed algorithm is better than that of any other algorithms.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.426-430
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• 1987

The reliability is the critical issue in many computer applications, particularly in process control system. In this paper we describe how to achieve the reliability improvement in controller system based multiprocessor. The proposed method is accomplished by using the techniques of fault detection, fault isolation, safe action, and fault diagnosis.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.5
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• pp.41-51
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• 1996

In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10a
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• pp.851-856
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• 1987

A direct computation algorithm of two dimensional fast Fourier transform (2D-FFT) is considered here for implementation in mesh connected multiprocessor array of both a 2D-toroidal and a rectangular type. Results are derived for a hardware algorithm including data allocation and interprocessor communications. A performance comparison is carried out between the proposed direct 2D-FFT computation and the conventional one to show that a new algorithm gives higher speedup under a reasonable assumption on the speeds of operations.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.927-936
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• 1988

This paper proposes a pipelined memory access method as a new technique for a bus interface between processors and memories in tightly coupled multiprocessor systems. Since the shared bus is bottle neck of the system, model of pipelined access to memory has been developed. Results of the evaluation by the discrete time Markov model showed a significant improvement of the efficiency.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.430-433
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• 1999

Woo[8]proposed dual-token based fault-tolerant scheduling algorithm in multiprocessor environment for resolving the problem of old systems that have a central dispatcher processor. However, this algorithm does not present token allocation algorithm in detail when central dispatcher processor has failed. In this paper, we propose a fault detection algorithm and processor selection algorithm for token allocation when central dispatcher processor has failed.

• Journal of the Korea Society for Simulation
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• v.1 no.1
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• pp.87-102
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• 1992

This paper presents the development of event-driven system level simulation tool SMPLE(Smpl Extende, an extention fo smpl) and its application to the performance analysis of multiprocessor computer systems. Because of its data structure, it is very difficult to change, expand or add new functions to simulation language smpl implemented by MacDougall. In SMPLE, we change data structure with structure and pointer, add new functions, and enable dynamic memory management. Using new data structure, facilities, and functions added in SMPLE, we simulate job processing of a shared bus multiprocessor system with autonomous hierarchical I/O subsystem. We set system performance contribution of subsystems and units. The impact of disk I/O on system performance is evaluated under vairous conditions of number of processors, processing power, memory access time and disk seek time.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.27 no.4
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• pp.42-48
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• 2004

This paper concerns on a multiprocessor task scheduling problem with precedence relation, in which each task requires several processors simultaneously. Meta-heuristic generally finds a good solution if it starts from a good solution. In this paper, a tabu search is presented to find a schedule of minimal time to complete all tasks. A modified tabu search is also presented which uses a new initial solution based on the best solution during the previous run as the new starting solution for the next iteration. Numerical results show that a tabu search and a modified tabu search yield a better performance than the previous studies.

• Journal of Korea Multimedia Society
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• v.8 no.12
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• pp.1605-1612
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• 2005

This paper presents the knowledge and experience we obtained by employing multiprocessor systems as a computer simulation design verification to study high-performance computing system. This paper also describes a case study of symmetric multiprocessors (SMP) kernel on a 32 CPUs CC-NUMA architecture using an actual architecture. A small group of CPUs of CC-NUMA, high-performance computer system, is clustered into a processing node or cluster. By simulating the system design verification tools; we discussed SMP OS kernel on a CC-NUMA multiprocessor architecture performance which is $32\%$ of the total execution time and remote memory access latency is occupied $43\%$ of the OS time. In this paper, we demonstrated our simulation results for multiprocessor, high-performance computing system performance, using simulation-based design verification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.97-102
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• 2014

Abdelzaher et al. proposed an algorithm to determine the schedulability of aperiodic tasks on multiprocessor systems, and proved that the aperiodic tasks are schedulable if the upperbound of synthetic utilization is less than or equal to 0.59. But this algorithm has a drawback in that if some tasks, even though they are completed and have no more execution times, are included in the current invocation set, their execution times and deadlines are added to the synthetic utilization. This may lead to a problem in which actually schedulable tasks are decided not to be schedulable. In this paper, we recognize the above mentioned problem and propose an improved synthetic utilization method that can be used to schedule aperiodic tasks more efficiently on multiprocessor systems.