• 한국멀티미디어학회논문지
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• 제9권1호
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• pp.119-126
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• 2006

멀티 프로세서 시스템에서 스케쥴링은 매우 중요한 부분이지만, 최적의 해를 구하는 것이 복잡하여 최근 다양한 휴리스틱 방법들에 의한 스케쥴링 알고리즘들이 제안되고 있다. 본 논문에서는 유전 알고리즘을 이용한 새로운 스케쥴링 알고리즘을 제시한다. 또한, 해를 구하는 과정에서 시뮬레이티드 어닐링 (simulated annealing)의 확률을 이용하여 유전 알고리즘의 성능을 개선시킨다. 제시된 알고리즘은 태스크들의 최종 수행 완료 시간 (makespan)을 최소화하는 것을 목표로 한다. 모의 실험을 통하여 제시된 알고리즘이 다른 알고리즘보다 최종 수행 완료 시간이 작음을 확인할 수 있었다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.426-430
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• 1987

The reliability is the critical issue in many computer applications, particularly in process control system. In this paper we describe how to achieve the reliability improvement in controller system based multiprocessor. The proposed method is accomplished by using the techniques of fault detection, fault isolation, safe action, and fault diagnosis.

• 전자공학회논문지B
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• 제33B권5호
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• pp.41-51
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• 1996

In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집(한일합동학술편); 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.851-856
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• 1987

A direct computation algorithm of two dimensional fast Fourier transform (2D-FFT) is considered here for implementation in mesh connected multiprocessor array of both a 2D-toroidal and a rectangular type. Results are derived for a hardware algorithm including data allocation and interprocessor communications. A performance comparison is carried out between the proposed direct 2D-FFT computation and the conventional one to show that a new algorithm gives higher speedup under a reasonable assumption on the speeds of operations.

• 대한전자공학회논문지
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• 제25권8호
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• pp.927-936
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• 1988

This paper proposes a pipelined memory access method as a new technique for a bus interface between processors and memories in tightly coupled multiprocessor systems. Since the shared bus is bottle neck of the system, model of pipelined access to memory has been developed. Results of the evaluation by the discrete time Markov model showed a significant improvement of the efficiency.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.430-433
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• 1999

Woo[8]proposed dual-token based fault-tolerant scheduling algorithm in multiprocessor environment for resolving the problem of old systems that have a central dispatcher processor. However, this algorithm does not present token allocation algorithm in detail when central dispatcher processor has failed. In this paper, we propose a fault detection algorithm and processor selection algorithm for token allocation when central dispatcher processor has failed.

• 한국시뮬레이션학회논문지
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• 제1권1호
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• pp.87-102
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• 1992

This paper presents the development of event-driven system level simulation tool SMPLE(Smpl Extende, an extention fo smpl) and its application to the performance analysis of multiprocessor computer systems. Because of its data structure, it is very difficult to change, expand or add new functions to simulation language smpl implemented by MacDougall. In SMPLE, we change data structure with structure and pointer, add new functions, and enable dynamic memory management. Using new data structure, facilities, and functions added in SMPLE, we simulate job processing of a shared bus multiprocessor system with autonomous hierarchical I/O subsystem. We set system performance contribution of subsystems and units. The impact of disk I/O on system performance is evaluated under vairous conditions of number of processors, processing power, memory access time and disk seek time.

• 산업경영시스템학회지
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• 제27권4호
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• pp.42-48
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• 2004

This paper concerns on a multiprocessor task scheduling problem with precedence relation, in which each task requires several processors simultaneously. Meta-heuristic generally finds a good solution if it starts from a good solution. In this paper, a tabu search is presented to find a schedule of minimal time to complete all tasks. A modified tabu search is also presented which uses a new initial solution based on the best solution during the previous run as the new starting solution for the next iteration. Numerical results show that a tabu search and a modified tabu search yield a better performance than the previous studies.

• 한국멀티미디어학회논문지
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• 제8권12호
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• pp.1605-1612
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• 2005

This paper presents the knowledge and experience we obtained by employing multiprocessor systems as a computer simulation design verification to study high-performance computing system. This paper also describes a case study of symmetric multiprocessors (SMP) kernel on a 32 CPUs CC-NUMA architecture using an actual architecture. A small group of CPUs of CC-NUMA, high-performance computer system, is clustered into a processing node or cluster. By simulating the system design verification tools; we discussed SMP OS kernel on a CC-NUMA multiprocessor architecture performance which is $32\%$ of the total execution time and remote memory access latency is occupied $43\%$ of the OS time. In this paper, we demonstrated our simulation results for multiprocessor, high-performance computing system performance, using simulation-based design verification.

• 한국정보통신학회논문지
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• 제18권1호
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• pp.97-102
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• 2014

다중프로세서 시스템에서 임의의 시점에 비주기 태스크들의 스케줄링 가능성을 판단하기위한 알고리즘으로서 합성 이용율이 Abdelzaher등에 의해 제시되었는데, 이들은 임의의 시점에 합성이용율의 상한 값인 0.59를 넘지 않으면 비주기 태스크들이 스케줄링 가능 하다는 것을 증명 하였다. 하지만 이 방법은 비주기 태스크들의 프로세서 이용율 계산 시 태스크가 실제 모든 실행시간을 종료하여 더 이상의 실행시간을 갖지 않더라도 현재요청집합에 속해 있다면 실행시간과 종료시한을 합성 이용율에 포함하기 때문에 스케줄링 가능한 태스크들이 실행 불가능한 경우로 판단되는 문제점을 가지고 있다. 본 논문에서는 이러한 문제점을 해결하여 다중프로세서 시스템에서 더 많은 비주기 태스크들이 스케줄링 가능 하도록 개선된 합성 이용율 방법을 제시하였다.